Motorola Single Board Computer 用户手册
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Programming the MVME51xx
Introduction
This chapter provides basic information useful in programming the
MVME51xx. This includes a description of memory maps, control and
status registers, PCI arbitration, interrupt handling, sources of reset, and
big/little-endian issues.
MVME51xx. This includes a description of memory maps, control and
status registers, PCI arbitration, interrupt handling, sources of reset, and
big/little-endian issues.
For additional programming information about the MVME510x, refer to
the MVME5100-Series Single Board Computer Programmer’s Reference
Guide.
the MVME5100-Series Single Board Computer Programmer’s Reference
Guide.
For programming information about the PMCs, refer to the applicable
user’s manual furnished with the PMCs.
user’s manual furnished with the PMCs.
Memory Maps
There are multiple buses on the MVME510x and each bus domain has its
own view of the memory map. The following sections describe the
MVME510x memory organization from the following three points of
view:
own view of the memory map. The following sections describe the
MVME510x memory organization from the following three points of
view:
❏
The mapping of all resources as viewed by the MPU (processor bus
memory map)
memory map)
❏
The mapping of onboard resources as viewed by PCI local bus
masters (PCI bus memory map)
masters (PCI bus memory map)
❏
The mapping of onboard resources as viewed by VMEbus masters
(VMEbus memory map)
(VMEbus memory map)
Additional, more detailed memory maps can be found in the MVME5100-
Series Single Board Computer Programmer’s Reference Guide.
Series Single Board Computer Programmer’s Reference Guide.