Panasonic MN103001G/F01K 用户手册
Bus Controller (BC)
8-50
Fig. 8-13-22
Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Multiplex Mode (MCLK = SYSCLK)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
“Description of Registers.”
MCLK
SYSCLK
AS
CS2
BCE
ASA
RWSEL
A23* to 16
ADM15 to 0
RE
WEn
EA
ASN
ASA
ADE
EA
REN
Write
Read
DK
DW
BCE
WEN
DW
DK detection start
DK detection start
addr
ADE
ASN
Consumed internally
by the BC
by the BC
Consumed internally
by the BC
by the BC
data in
addr
addr
addr
: Undefined
data out
“0”( )
“L”
*
“0”( )
“L”
: A23 also serves as CS3
: Undefined or Hi-Z