Intel IXP42X 用户手册
Intel
®
IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM
September 2006
272
Order Number: 252480-006US
6.14.2.25 PCI to AHB DMA Length Register 0
(PCI_PTADMA0_LENGTH)
6.14.2.26 PCI to AHB DMA AHB Address Register 1
(PCI_PTADMA1_AHBADDR)
Register
PCI_PTADMA0_PCIADDR
Bits
Name
Description
Reset
Value
PCI Access
AHB Access
31:2
address
PCI word address
0x00000000
RO
RW
1:0
Lower PCI address bits hard-wired to zero.
00
RO
RO
Register Name:
PCI_PTADMA0_LENGTH
Hex Offset Address:
0xC0000060
Reset Hex Value:
0x00000000
Register
Description:
Provides word count and control for PCI to AHB DMA transfers. Paired with pci_ptadma1_length to allow
buffering of DMA transfer requests.
Access: See below.
31 30 29 28 27
16 15
0
EN
(Rsvd)
BE
(Reserved)
wordcount
Register
PCI_PTADMA0_LENGTH
Bits
Name
Description
Reset
Value
PCI Access
AHB Access
31
EN
Channel enable. When set to a 1, executes a DMA
transfer if wordcount is nonzero. When 0, the channel
is disabled. Hardware clears this bit when the DMA
transfer is complete.
0
RO
RW
30:2
9
(Reserved). Read as 0.
00
RO
RO
28
DS
Data Swap indicator. When set to a 1, data from the
PCI bus is byte swapped before being sent to the AHB
bus. When 0, no swapping is done.
0
RO
RW
27:1
6
(Reserved). Read as 0.
0x000
RO
RO
15:0
wordcount
Number of words to transfer.
0x0000
RO
RW
Register Name:
PCI_PTADMA1_AHBADDR
Hex Offset Address:
0xC0000064
Reset Hex Value:
0x00000000
Register
Description:
Destination address on the AHB bus for PCI to AHB DMA transfers. Paired with pci_ptadma0_ahbaddr to
allow buffering of DMA transfer requests.
Access: See below.
31
2
1
0
address
0
0