takeMS Ddr 512mb / 400 PC3200 TakeMS Bulk 14527 产品数据表
产品代码
14527
3
3
2
2
/
/
6
6
4
4
M
M
x
x
6
6
4
4
b
b
i
i
t
t
s
s
184PIN
PC3200
DDR
SDRAM
DIMM
184PIN PC3200 DDR SDRAM DIMM
Serial Presence Detect
256M Bytes for Unbuffered & Non ECC Module (DDR400 use 32Mx8 *8pcs)
Byte
No.
Description Function
Hex
Value
0
Number of Serial PD Bytes used
128 bytes
80h
1
Total number of Bytes in Serial PD device
256 bytes
08h
2
Fundamental Memory Type
DDR SDRAM
07h
3
# of Row Addresses on this assembly
13
0Dh
4
# of Column Addresses on this assembly
10
0Ah
5
# of Physical Banks on DIMM
1 ROWS
01h
6
Data Width of this assembly
64 bit
40h
7
Data Width of this assembly(Continued)
0
00h
8
Voltage Interface Level of this assembly
SSTL_2.5V
04h
9
DDRAM Cycle time at CAS Latency=2.5
5 ns
50h
10
DDRAM Access from Clock at CAS Latency=2.5
+/- 0.7 ns
70h
11
DIMM configuration type(Non-parity, Parity or ECC)
Non-parity
00h
12
Refresh Rate/Type
7.8 us
82h
13
Primary SDRAM Width
X8 bit
08h
14
Error Checking SDRAM Width
None
00h
15
Min. Clock Delay, Back-to-Back Random Column Access
Tccd=1 clk
01h
16 Burst
Lengths
Supported 2,4,8
0eh
17
Number of Banks on SDRAM Device
4 Banks
04h
18 CAS
Latency
2.5
08h
19
Chip Select Latency
0 clk
01h
20
Write Latency
1 clk
02h
21 DDR
SDRAM
Module
Attributes
Unbuffer
20h
22
DDRAM Device Attributes: General
+/- 0.2v voltage
tolerance
00h
23
DDRAM Cycle time at CAS Latency=2
7.5ns
75h
24
DDRAM Access from Clock at CAS Latency=2
+/- 0.7 ns
70h
25
DDRAM Cycle time at CAS Latency=1.5
None
00h
26
DDRAM Access from Clock at CAS Latency=1.5
None
00h
27
Minimum Row Precharge Time (tRP)
15 ns
3Ch
28
Minimum Row Active to Row Active delay (tRRD)
10 ns
28h
29
Minimum RAS to CAS delay (tRCD)
15 ns
3Ch
30
Minimum Active to Precharge Time (tRAS)
40 ns
28h
31
Module Bank Density
256M of 1 row
40h
32
Address and Command Input Setup Time Before Clock
0.6 ns
60h
33
Address and Command Input Hold Time After Clock
0.6 ns
60h
34
Data/Data Mask Input Setup Time Before Data Strobe
0.4 ns
40h
35
Data/Data Mask Input Hold Time After Data Strobe
0.4 ns
40h
36-40 Reserved
Reserved
00h
41
Minimum active /auto-refresh time(tRC)
55 ns
37h
42
Minimum auto-refresh to active command period (tRFC)
70 ns
46h
43
Maximum cycle time(Tck max)
10 ns
28h
44
Maximum DQS-DQ skew time(tDQSQ)
0.4 ns
28h
45
Maximum read data hold skew factor(tQHS)
0.50 ns
50h
46-61 Reserved
Reserved
00h
62 SPD
Revision
Rev0.0
00h
63
Checksum for Bytes 0-62
-
BDh
64-71 Manufacturer’s JEDEC ID Code
-
7F, 7F, 7F, 58h
72
Module Manufacturing Location
-
31h
73-90 Module Part Number
BD256TEC400
42, 44, 32, 35, 36,
54, 45, 43, 34, 30,
54, 45, 43, 34, 30,
30h
91-92 Module Revision Code
Reserved
00h
93-94 Module Manufacturing Date
YY-WW
-
95-98 Module
Serial
Number
Reserved
00h
99-127 Manufacturer’s Specific Data
Reserved
00h
128-255 Open for customer use
Reserved
00h