Texas Instruments TMS320DM357 用户手册
4.64 Count 0 Register (COUNT0)
4.65 Receive Count Register (RXCOUNT)
Registers
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The Count 0 Register (COUNT0) is shown in
and described in
.
Figure 79. Count 0 Register (COUNT0)
15
7
6
0
Reserved
EP0RXCOUNT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 80. Count 0 Register (COUNT0) Field Descriptions
Bit
Field
Value
Description
15-7
Reserved
0
Reserved
6-0
EP0RXCOUNT
0-7Fh
Indicates the number of received data bytes in the Endpoint 0 FIFO. The value returned changes as
the contents of the FIFO change and is only valid while RXPKTRDY of PERI_CSR0 or
HOST_CSR0 is set.
the contents of the FIFO change and is only valid while RXPKTRDY of PERI_CSR0 or
HOST_CSR0 is set.
The Receive Count Register (RXCOUNT) is shown in
and described in
.
Figure 80. Receive Count Register (RXCOUNT)
15
13
12
0
Reserved
EPRXCOUNT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 81. Receive Count Register (RXCOUNT) Field Descriptions
Bit
Field
Value
Description
15-13
Reserved
0
Reserved
12-0
EPRXCOUNT
0-1FFFh
Holds the number of received data bytes in the packet in the Receive FIFO. The value
returned changes as the contents of the FIFO change and is only valid while RXPKTRDY of
PERI_RXCSR or HOST_RXCSR is set.
returned changes as the contents of the FIFO change and is only valid while RXPKTRDY of
PERI_RXCSR or HOST_RXCSR is set.
Universal Serial Bus (USB) Controller
128
SPRUGH3 – November 2008