Texas Instruments TMS320DM357 用户手册
3.3
DMA Operation
3.3.1
DMA Transmit Operation
3.3.1.1
Transmit Buffer
3.3.1.2
CPPI Transmit Buffer Descriptor
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USB Controller Host and Peripheral Modes Operation
3.2.4.2.2
Operation
The operation starts when the software writes to the FIFO and sets TXPKTRDY bit of HOST_TXCSR
(bit 0). This triggers the controller to send an OUT token followed by the first data packet from the FIFO.
(bit 0). This triggers the controller to send an OUT token followed by the first data packet from the FIFO.
An interrupt is generated whenever a packet is sent and the software may use this interrupt to load the
next packet into the FIFO and set the TXPKTRDY bit in the HOST_TXCSR register (bit 0) in the same
way as for a Bulk Tx endpoint. As the interrupt could occur almost any time within a frame, depending on
when the host has scheduled the transaction, this may result in irregular timing of FIFO load requests. If
the data source for the endpoint is coming from some external hardware, it may be more convenient to
wait until the end of each frame before loading the FIFO as this will minimize the requirement for
additional buffering. This can be done by using the SOF_PULSE signal from the controller to trigger the
loading of the next data packet. The SOF_PULSE is generated once per frame(/microframe). The
interrupts may still be used to set the TXPKTRDY bit in HOST_TXCSR.
next packet into the FIFO and set the TXPKTRDY bit in the HOST_TXCSR register (bit 0) in the same
way as for a Bulk Tx endpoint. As the interrupt could occur almost any time within a frame, depending on
when the host has scheduled the transaction, this may result in irregular timing of FIFO load requests. If
the data source for the endpoint is coming from some external hardware, it may be more convenient to
wait until the end of each frame before loading the FIFO as this will minimize the requirement for
additional buffering. This can be done by using the SOF_PULSE signal from the controller to trigger the
loading of the next data packet. The SOF_PULSE is generated once per frame(/microframe). The
interrupts may still be used to set the TXPKTRDY bit in HOST_TXCSR.
The DMA controller sub-module is a common 4 dual-channel DMA controller. It supports 4 TX and 4 RX
channels, and each channel attaches to the associated endpoint in the controller. Channel 0 maps to
Endpoint 1 up to Channel 3 mapping to Endpoint 4, while endpoint 0 cannot utilize the DMA. The DMA is
programmed through parameters stored in the DMA registers, and implements DMAs through the buffer
descriptor chains stored in main memory. The DMA utilizes incrementing addressing mode, and can burst
up to 64 bytes. When a DMA is initiated, the DMA controller reads the current parameters for that channel
from the DMA registers, reads the CPPI buffer descriptor pointed to by the parameters, and performs the
DMA using the data buffer in the descriptor. The DMA controller updates and saves the DMA parameters
when the data is completed. The software can access the current parameters at any time by accessing
the DMA registers.
channels, and each channel attaches to the associated endpoint in the controller. Channel 0 maps to
Endpoint 1 up to Channel 3 mapping to Endpoint 4, while endpoint 0 cannot utilize the DMA. The DMA is
programmed through parameters stored in the DMA registers, and implements DMAs through the buffer
descriptor chains stored in main memory. The DMA utilizes incrementing addressing mode, and can burst
up to 64 bytes. When a DMA is initiated, the DMA controller reads the current parameters for that channel
from the DMA registers, reads the CPPI buffer descriptor pointed to by the parameters, and performs the
DMA using the data buffer in the descriptor. The DMA controller updates and saves the DMA parameters
when the data is completed. The software can access the current parameters at any time by accessing
the DMA registers.
The DMA controller has a concept of DMA packets which is different from the USB packets. A DMA
packet can be (but not necessarily) of the same size as USB packet. Each DMA packet can comprise of
one or multiple data buffers. Each DMA channel can process one or multiple chains of these DMA
packets.
packet can be (but not necessarily) of the same size as USB packet. Each DMA packet can comprise of
one or multiple data buffers. Each DMA channel can process one or multiple chains of these DMA
packets.
The controller supports two modes of DMA: transparent mode and RNDIS mode. Transparent mode will
interrupt the CPU for every USB data packet, while RNDIS mode can service multiple USB packets with
only a single CPU interrupt.
interrupt the CPU for every USB data packet, while RNDIS mode can service multiple USB packets with
only a single CPU interrupt.
For transmit operation, the software has to program the DMA channel with a chain of transmit buffers.
A Transmit buffer is a contiguous block of memory used to store data for transmission. Each Tx buffer has
a corresponding Tx buffer descriptor. Each Tx buffer can be linked together with other Tx buffers to make
a DMA packet or a queue of DMA packets.
a corresponding Tx buffer descriptor. Each Tx buffer can be linked together with other Tx buffers to make
a DMA packet or a queue of DMA packets.
Transmit buffers are byte aligned structures located in processor’s main memory. Tx buffer size may vary
from 1 to 65,535 bytes.
from 1 to 65,535 bytes.
Tx buffer descriptors provide information about a single corresponding Tx data buffer. Every Tx buffer has
a single Tx buffer descriptor that stores the following information:
a single Tx buffer descriptor that stores the following information:
•
Pointer to the data buffer
•
Pointer to the next buffer descriptor in the queue
•
Buffer length and offset to the first valid byte of buffer data
•
Start of DMA packet (SOP) indicator
•
End of DMA packet (EOP) indicator
•
Ownership (only valid with SOP)
SPRUGH3 – November 2008
Universal Serial Bus (USB) Controller
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