Texas Instruments TMS320DM357 用户手册
3.4.1
USB Core Interrupts
3.4.2
DMA Interrupts
3.5
Test Modes
USB Controller Host and Peripheral Modes Operation
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There are two methods available for software to access USB core interrupts, selectable by the UINT bit of
CTRLR. The UINT bit cleared to 0 selects the PDR 2.0 compliant register set (INTSRCR, INTSETR,
INTCLRR, INTMSKR, INTMSKSETR, INTMSKCLRR, INTMASKEDR). This is the default, and should be
used for most systems. The DRVVBUS level change interrupt is only available in the PDR compliant
register. UINT set to one selects direct access to the USB core interrupt registers (INTRUSB, INTRUSBE,
INTRTX, INTRRX). Software should select a single method for interrupts and use its corresponding
registers exclusively.
CTRLR. The UINT bit cleared to 0 selects the PDR 2.0 compliant register set (INTSRCR, INTSETR,
INTCLRR, INTMSKR, INTMSKSETR, INTMSKCLRR, INTMASKEDR). This is the default, and should be
used for most systems. The DRVVBUS level change interrupt is only available in the PDR compliant
register. UINT set to one selects direct access to the USB core interrupt registers (INTRUSB, INTRUSBE,
INTRTX, INTRRX). Software should select a single method for interrupts and use its corresponding
registers exclusively.
Interrupt status can be determined using the INTSRCR (interrupt source) register. This register is
non-masked. To clear the interrupt source, set the corresponding interrupt bit in INTCLRR register. For
debugging purposes, interrupt can be set manually through INTSETR register.
non-masked. To clear the interrupt source, set the corresponding interrupt bit in INTCLRR register. For
debugging purposes, interrupt can be set manually through INTSETR register.
The interrupt controller provides the option of masking the interrupts. A mask can be set using
INTMSKSETR register and can be cleared by setting the corresponding bit in the INTMSKCLRR register.
The mask can be read from INTMSKR register. The masked interrupt status is determined using the
INTMASKEDR register.
INTMSKSETR register and can be cleared by setting the corresponding bit in the INTMSKCLRR register.
The mask can be read from INTMSKR register. The masked interrupt status is determined using the
INTMASKEDR register.
Software should write all zeros to the End Of Interrupt Register (EOIR) to acknowledge the completion of
the USB core interrupt.
the USB core interrupt.
Note:
If the EOIR is not written, the interrupt output to the CPU will not be pulsed again for the next
interrupt.
interrupt.
Interrupt status for the DMA interrupts is determined by TCCPIRAWSR and RCPPIRAWSR registers.
These are the raw interrupt status registers for DMA interrupts.
These are the raw interrupt status registers for DMA interrupts.
Tx DMA interrupts mask is set using TCPPIENSETR register and cleared using TCPPIIENCLRR register.
The masked status is read using TCPPIMSKSR register.
The masked status is read using TCPPIMSKSR register.
Rx DMA interrupts mask is set using RCPPIENSETR register and cleared using RCPPIIENCLRR register.
The masked status is read using RCPPIMSKSR register.
The masked status is read using RCPPIMSKSR register.
Like USB core interrupts, the CPPIEOIR register needs to be written by the host processor software to
acknowledge the completion of the interrupt.
acknowledge the completion of the interrupt.
Upon receipt of a DMA interrupt, software should check TCPPIRAWSR/RCPPIRAWSR to determine
which DMA channel(s) to service. Check the CPPI buffer descriptor ownership field for the completed
channel for error conditions and add or update buffer descriptors as needed. Write the RCPPICOMPPTR
or TCPPICOMPPTR completion pointer with the address of the buffer descriptor serviced in order to clear
the interrupt. Finally, write the DMA End Of Interrupt register CPPIEOIR with all zeros to enable future (or
current unserviced) interrupts to pulse the interrupt output to the CPU.
which DMA channel(s) to service. Check the CPPI buffer descriptor ownership field for the completed
channel for error conditions and add or update buffer descriptors as needed. Write the RCPPICOMPPTR
or TCPPICOMPPTR completion pointer with the address of the buffer descriptor serviced in order to clear
the interrupt. Finally, write the DMA End Of Interrupt register CPPIEOIR with all zeros to enable future (or
current unserviced) interrupts to pulse the interrupt output to the CPU.
When using DMA with a TX endpoint, set the TXCSR register DMAMODE bit to one in order to receive
only error (not packet completion) interrupts. For DMA with an RX endpoint, the DMAMODE bit in RXCSR
should be cleared to 0.
only error (not packet completion) interrupts. For DMA with an RX endpoint, the DMAMODE bit in RXCSR
should be cleared to 0.
The controller supports the four USB 2.0 test modes defined for High-speed functions. It also supports an
additional “FIFO access” test mode that can be used to test the operation of the CPU interface, the DMA
controller (if configured) and the RAM block.
additional “FIFO access” test mode that can be used to test the operation of the CPU interface, the DMA
controller (if configured) and the RAM block.
The test modes are entered by writing to the TestMode register (offset address 0x40F). At test mode is
usually requested by the host sending a SET_FEATURE request to Endpoint 0. When the software
receives the request, it should wait until the Endpoint 0 transfer has completed (when it receives the
Endpoint 0 interrupt indicating the status phase has completed) then write to the TestMode register.
usually requested by the host sending a SET_FEATURE request to Endpoint 0. When the software
receives the request, it should wait until the Endpoint 0 transfer has completed (when it receives the
Endpoint 0 interrupt indicating the status phase has completed) then write to the TestMode register.
Note:
These test modes have no purpose in normal operation.
70
Universal Serial Bus (USB) Controller
SPRUGH3 – November 2008