Texas Instruments TMS320DM357 用户手册
4.16 CPPI DMA End of Interrupt Register (CPPIEOIR)
Registers
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Note:
This register was previously named TCPPIEOIR, and that name will continue to exist in the
CSL for backward compatibility.
CSL for backward compatibility.
The CPPI DMA End of Interrupt Register (CPPIEOIR) is shown in
and described in
.
Figure 31. CPPI DMA End of Interrupt Register (CPPIEOIR)
31
16
Reserved
R-0
15
8
7
0
Reserved
VECTOR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. CPPI DMA End of Interrupt Register (CPPIEOIR) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
VECTOR
0-FFh
End of Interrupt Vector
This is an application specific register which is essentially a general purpose output from the LCSAR.
One cycle after this register is written, the eoi_vector[7:0] value will appear on the eoi_vector output port
from the LCSAR and the eoi_write output port will be asserted for 1 clock cycle. This register is used to
convert level sensitive interrupts to pulsed, non-redundant interrupts. Software should write all zeros for
the vector value.
One cycle after this register is written, the eoi_vector[7:0] value will appear on the eoi_vector output port
from the LCSAR and the eoi_write output port will be asserted for 1 clock cycle. This register is used to
convert level sensitive interrupts to pulsed, non-redundant interrupts. Software should write all zeros for
the vector value.
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SPRUGH3 – November 2008