Intel 82559 用户手册
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
127
Physical Layer Interface
7.3.6
100BASE-TX Receive Error Frame Counter: Register 21
7.3.7
Receive Symbol Error Counter: Register 22
7.3.8
100BASE-TX Receive EOF Error Counter: Register 23
7.3.9
10BASE-T Receive EOF Error Counter: Register 24
7.3.10
10BASE-T Transmit Jabber Detect Counter: Register 25
Bit
Name
R / W
Description
Default
15:0
Receive Error Frame
RO
SC
SC
This register contains a 16-bit counter for receive
error frames. It is incremented for frames with a
receive error condition (frames containing a symbol
error or frames with a premature end of frame).
When the counter is full, additional error frames are
not counted. This counter is self-clearing on read.
error frames. It is incremented for frames with a
receive error condition (frames containing a symbol
error or frames with a premature end of frame).
When the counter is full, additional error frames are
not counted. This counter is self-clearing on read.
0
Bit
Name
R / W
Description
Default
15:0
Symbol Error
RO
SC
SC
This register contains a 16-bit counter and
increments for each symbol error. The counter stop
counting additional symbol errors when it is full.
This counter is self-clearing on read.
increments for each symbol error. The counter stop
counting additional symbol errors when it is full.
This counter is self-clearing on read.
0
Bit
Name
R / W
Description
Default
15:0
Premature End of Frame
RO
SC
SC
This register contains a 16-bit counter and
increments for each premature end of frame event.
It stops counting additional premature end of frame
events when it is full. It is self-clearing on read.
increments for each premature end of frame event.
It stops counting additional premature end of frame
events when it is full. It is self-clearing on read.
0
Bit
Name
R / W
Description
Default
15:0
End of Frame
RO
SC
SC
This register is a 16-bit counter that increments for
each end of frame error event. The counter stops
counting additional errors when it is full. It is self-
clearing on read.
each end of frame error event. The counter stops
counting additional errors when it is full. It is self-
clearing on read.
0
Bit
Name
R / W
Description
Default
15:0
Jabber Detect
RO
SC
SC
This register is a 16-bit counter that increments for
each jabber detection event. The counter stops
counting additional events when it is full. It is self-
clearing on read.
each jabber detection event. The counter stops
counting additional events when it is full. It is self-
clearing on read.
0