Intel 82559 用户手册
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
25
EEPROM Interface
5
The 8255x has a local memory interface that provides access to a serial EEPROM and optional
Flash device. All controllers implement these interfaces using multiplexed pins. Since the interface
uses multiplexed pins, it is not simultaneously available to software. Thus, software cannot read the
EEPROM at the same time as it is reading Flash memory. However, software can certainly read the
EEPROM at the same time as it is reading Flash memory. However, software can certainly read the
EEPROM and then read Flash memory or vice versa.
The Serial EEPROM stores configuration data (such as the Ethernet MAC address) for the 8255x.
The EEPROM is a serial in and serial out device. The 82557 and 82558 support a single size of
EEPROM that contains 64 registers of 16 bits per register. The 82559 and later generation devices
EEPROM that contains 64 registers of 16 bits per register. The 82559 and later generation devices
support either a 64 register EEPROM or a 256 register EEPROM.
Software may read or write to the EEPROM by accessing the EEPROM port in the 8255x.
All accesses, read or write, are preceded by a command instruction to the device. The command
instructions, begin with a logical 1 as a start bit, two opcode bits (indicating read, write, erase, etc.),
and n-bits of address. The address field is 6 bits for a 64-register EEPROM and 8 bits for a 256-
and n-bits of address. The address field is 6 bits for a 64-register EEPROM and 8 bits for a 256-
register EEPROM. The end of the address field is indicated by a “dummy 0” bit from the
EEPROM, which indicates the entire address field has been transferred to the device. A command
is issued by asserting the chip select signal and clocking the data into the EEPROM on its data
is issued by asserting the chip select signal and clocking the data into the EEPROM on its data
input pin relative to the serial clock input. The chip select signal is de-asserted after completion of
the EEPROM cycle (Command, Address and Data).
The 8255x performs an automatic read of several registers in the EEPROM following the de-
assertion of the PCI Reset signal. The controllers automatically read the EEPROM to properly set
assertion of the PCI Reset signal. The controllers automatically read the EEPROM to properly set
several power-on default configurations. Since the 82559 and later devices are capable of
interfacing with different size EEPROMs (64 or 256 words), software determine the EEPROM size
first using the “dummy zero mechanism” before it accesses the EEPROM after a reset.
first using the “dummy zero mechanism” before it accesses the EEPROM after a reset.