Nxp Semiconductors PIP3119-P 用户手册

Philips Semiconductors

Product specification

 Logic level TOPFET

PIP3119-P 

 

 

The supply for the logic and overload protection is taken from the input.
Limits are for -40˚C 

≤

 T

mb

 

≤

 150˚C; typicals are for T

mb

 = 25˚C unless otherwise specified

V

IS(TO)

Input threshold voltage

V

DS

 = 5 V; I

D

 = 1 mA

0.6

-

2.4

V

T

mb

 = 25˚C

1.1

1.6

2.1

V

I

IS

Input supply current

normal operation; 

V

IS

 = 5 V

100

220

400

µ

A

V

IS

 = 4 V

80

195

330

µ

A

I

ISL

Input supply current

protection latched; 

V

IS

 = 5 V

200

400

650

µ

A

V

IS

 = 3 V

130

250

430

µ

A

V

ISR

Protection reset voltage

1

reset time t

r

 

≥

 100 

µ

s

1.5

2

2.9

V

t

lr

Latch reset time

V

IS1

 = 5 V, V

IS2

 < 1 V

10

40

100

µ

s

V

(CL)IS

Input clamping voltage

I

I

 = 1.5 mA

5.5

-

8.5

V

R

IG

Input series resistance

2

T

mb

 = 25˚C

-

33

-

k

Ω

to gate of power MOSFET

T

mb

 = 25˚C; V

DD

 = 13 V; resistive load R

L

 = 4 

Ω

.  Refer to waveform figure and test circuit.

t

d on

Turn-on delay time

V

IS

 = 5 V

-

25

50

µ

s

t

r

Rise time

-

50

100

µ

s

t

d off

Turn-off delay time

V

IS

 = 0 V

-

60

120

µ

s

t

f

Fall time

-

50

100

µ

s

1 The input voltage below which the overload protection circuits will be reset.

2 Not directly measureable from device terminals.

May 2001

4

Rev 1.000