Motorola CPCI-6115 用户手册
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Functional Description
MV64360 System Controller
74
the second function, the controller is used by the system software to read the contents of the
VPD EEPROM contained on the CPCI-6115 board, along with the SPD EEPROMs for the
onboard memory banks, to further initialize the memory controller and other interfaces. See the
programming model section of this document for more information including I
VPD EEPROM contained on the CPCI-6115 board, along with the SPD EEPROMs for the
onboard memory banks, to further initialize the memory controller and other interfaces. See the
programming model section of this document for more information including I
2
C bus device
addressing.
The CPCI-6115 board has the following I
2
C serial devices connected to this I
2
C bus:
z
8 KB EEPROM for user defined MV64360 initialization
z
8 KB EEPROM for VPD
z
8 KB EEPROM for user data
z
Two 256-byte EEPROMs for SPD
z
DS1621 Temperature Sensor
The 8 KB devices are Atmel AT24C04N Serial EEPROMs.
4.3.4.12 Interrupt Controller
The CPCI-6115 uses the interrupt controller integrated into MV64360 to manage the MV64360
internal interrupts, as well as external interrupt requests. The interrupts are routed to the
MV64360 MPP pins from onboard resources as shown in
internal interrupts, as well as external interrupt requests. The interrupts are routed to the
MV64360 MPP pins from onboard resources as shown in
. The external
interrupt sources include the following:
z
Onboard PCI device interrupts
z
PMC slot interrupts
z
RTC interrupt
z
Watchdog timer interrupts
z
ABORT switch interrupt
z
External UART interrupts
z
CompactPCI interrupts
z
Ethernet PHY interrupts
For added information on external interrupt assignments, refer to the MCPN905 CompactPCI
Single Board Computer Programmer’s Reference Guide.
Single Board Computer Programmer’s Reference Guide.
4.3.4.13 PCI Bus Arbitration
PCI arbitration is performed by the MV64360 chip. The MV64360 integrates two PCI arbiters,
one for each PCI interface (PCI Bus 0.0/1.0). Each arbiter can handle up to six external agents
plus one internal agent (PCI Bus 0.0/1.0 master). The internal PCI arbiter REQ#/GNT# signals
are multiplexed on the MV64360 MPP pins. The internal PCI arbiter is disabled by default (the
MPP pins function as general purpose inputs). Software will configure the MPP pins to function
as request/grant pairs for the internal PCI arbiter. The arbitration pairs for the CPCI-6115 are
assigned to the MPP pins as shown in the following table.
one for each PCI interface (PCI Bus 0.0/1.0). Each arbiter can handle up to six external agents
plus one internal agent (PCI Bus 0.0/1.0 master). The internal PCI arbiter REQ#/GNT# signals
are multiplexed on the MV64360 MPP pins. The internal PCI arbiter is disabled by default (the
MPP pins function as general purpose inputs). Software will configure the MPP pins to function
as request/grant pairs for the internal PCI arbiter. The arbitration pairs for the CPCI-6115 are
assigned to the MPP pins as shown in the following table.