Motorola CPCI-6115 用户手册
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Functional Description
IDE Controller
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This bus is limited to 33 MHz PCI because the IDE controller is a 33 MHz-only device. PCI Bus
1.0 is compliant to PCI Revision 2.1. VIO is limited to +5 V only. Do not alter the location of
PMC1 keying pin.
1.0 is compliant to PCI Revision 2.1. VIO is limited to +5 V only. Do not alter the location of
PMC1 keying pin.
4.3.13
IDE Controller
The CPCI-6115 uses the CMD Technology PCI646U2 IDE Controller to provide a single IDE
channel for external storage devices. The IDE Controller supports ATA/33 transfer rates. This
IDE channel is routed to connector J5 for rear-panel I/O or to a transition module. The transition
module allows connection of an IDE hard disk or CompactFlash module.
channel for external storage devices. The IDE Controller supports ATA/33 transfer rates. This
IDE channel is routed to connector J5 for rear-panel I/O or to a transition module. The transition
module allows connection of an IDE hard disk or CompactFlash module.
The PCI646U2 PCI-IDE Controller is a 32-bit/33 MHz PCI device and is the limiting device when
determining the operating frequency of PCI bus 1.0.
determining the operating frequency of PCI bus 1.0.
4.3.14
Intel 21555 PCI-to-PCI Bridge
The CPCI-6115 uses the Intel 21555 PCI-to-PCI bridge, which is connected to PCI bus 1.0. The
21555 bridge is compliant to PCI Revision 2.2. The following are key features of the 21555:
21555 bridge is compliant to PCI Revision 2.2. The following are key features of the 21555:
z
Non-transparent PCI-to-PCI bridge
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Mixed-frequency bus operation (33/66 MHz PCI on either primary or secondary)
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CompactPCI hot-swap compliant
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Secondary bus arbiter (not used on CPCI-6115)
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+3.3 V I/O, +5 V tolerant
The 21555 provides a MicroWire serial ROM interface. On power-up or reset, the 21555 can
load its configuration registers from a serial EEPROM on this interface. A 512-byte (93LC66A)
device is present on the CPCI-6115 for this purpose.
load its configuration registers from a serial EEPROM on this interface. A 512-byte (93LC66A)
device is present on the CPCI-6115 for this purpose.
4.3.15
CompactPCI Bus
The CompactPCI bus interface is implemented using the 21555 bridge with a 32-bit secondary
data bus (local side - PCI bus 1.0) and a 64-bit primary data bus (CompactPCI side). The 21555
supports +3.3 V or +5 V signalling at the CompactPCI bus, allowing the CPCI-6115 to operate
in a +3.3 V or +5 V chassis.
data bus (local side - PCI bus 1.0) and a 64-bit primary data bus (CompactPCI side). The 21555
supports +3.3 V or +5 V signalling at the CompactPCI bus, allowing the CPCI-6115 to operate
in a +3.3 V or +5 V chassis.
The CPCI-6115 is designed for use in a CompactPCI peripheral slot, so the 21555 non-
transparent bridge is used. The CPCI-6115 receives the CompactPCI clock, reset and bus
grant signals, and generates bus requests and interrupts as a peripheral board.
transparent bridge is used. The CPCI-6115 receives the CompactPCI clock, reset and bus
grant signals, and generates bus requests and interrupts as a peripheral board.
The CPCI-6115 supports a 33/66 MHz PCI interface to the CompactPCI backplane.
4.3.16
PMC Slots
The CPCI-6115 CPU board contains four EIA-E700 AAAB connectors for each PMC slot.
These connectors provide a PCI interface to two IEEE P1386.1-compliant PMC slots.
Connectors J11-J13 and J21-J23 provide the PCI interface while J14 and J24 provide a user
I/O path from the PMC slots to the CompactPCI backplane. PMC user I/O signals are routed
These connectors provide a PCI interface to two IEEE P1386.1-compliant PMC slots.
Connectors J11-J13 and J21-J23 provide the PCI interface while J14 and J24 provide a user
I/O path from the PMC slots to the CompactPCI backplane. PMC user I/O signals are routed