Cypress CY7C1910BV18 用户手册

Document #: 38-05619 Rev. *F

Page 7 of 29

CQ

Echo Clock

CQ Referenced with Respect to C. This is a free - running clock and is synchronized to the Input clock 
for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings 
for the echo clocks is shown in the 

CQ

Echo Clock

CQ Referenced with Respect to C. This is a free - running clock and is synchronized to the Input clock 
for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings 
for the echo clocks is shown in the 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus 
impedance. CQ, CQ, and Q

[x:0] 

output impedance are set to 0.2 x RQ, where RQ is a resistor connected 

between ZQ and ground. Alternatively, this pin can be connected directly to V

DDQ

, which enables the 

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

− Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing 

in the DLL turned off operation differs from those listed in this data sheet.

TDO

Output

TDO for JTAG.

TCK

Input

TCK Pin for JTAG.

TDI

Input

TDI Pin for JTAG.

TMS

Input

TMS Pin for JTAG.

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/36M

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/72M

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/144M

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/288M

N/A

Not Connected to the Die. Can be tied to any voltage level.

V

REF

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and AC 
measurement points.

V

DD

Power Supply Power Supply Inputs to the Core of the Device. 

V

SS

Ground

Ground for the Device. 

V

DDQ

Power Supply Power Supply Inputs for the Outputs of the Device. 

 (continued)