Intel 253668-032US 用户手册
Vol. 3 10-3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
IPIs can be sent to other processors in the system or to the originating processor
(self-interrupts). When the target processor receives an IPI message, its local APIC
handles the message automatically (using information included in the message such
as vector number and trigger mode). See Section 10.7, “Issuing Interprocessor
Interrupts,” for a detailed explanation of the local APIC’s IPI message delivery and
acceptance mechanism.
The local APIC can also receive interrupts from externally connected devices through
the I/O APIC (see Figure 10-1). The I/O APIC is responsible for receiving interrupts
generated by system hardware and I/O devices and forwarding them to the local
APIC as interrupt messages.
(self-interrupts). When the target processor receives an IPI message, its local APIC
handles the message automatically (using information included in the message such
as vector number and trigger mode). See Section 10.7, “Issuing Interprocessor
Interrupts,” for a detailed explanation of the local APIC’s IPI message delivery and
acceptance mechanism.
The local APIC can also receive interrupts from externally connected devices through
the I/O APIC (see Figure 10-1). The I/O APIC is responsible for receiving interrupts
generated by system hardware and I/O devices and forwarding them to the local
APIC as interrupt messages.
Individual pins on the I/O APIC can be programmed to generate a specific interrupt
vector when asserted. The I/O APIC also has a “virtual wire mode” that allows it to
communicate with a standard 8259A-style external interrupt controller. Note that the
local APIC can be disabled (see Section 10.4.3, “Enabling or Disabling the Local
APIC”). This allows an associated processor core to receive interrupts directly from
an 8259A interrupt controller.
Both the local APIC and the I/O APIC are designed to operate in MP systems (see
Figures 10-2 and 10-3). Each local APIC handles interrupts from the I/O APIC, IPIs
from processors on the system bus, and self-generated interrupts. Interrupts can
vector when asserted. The I/O APIC also has a “virtual wire mode” that allows it to
communicate with a standard 8259A-style external interrupt controller. Note that the
local APIC can be disabled (see Section 10.4.3, “Enabling or Disabling the Local
APIC”). This allows an associated processor core to receive interrupts directly from
an 8259A interrupt controller.
Both the local APIC and the I/O APIC are designed to operate in MP systems (see
Figures 10-2 and 10-3). Each local APIC handles interrupts from the I/O APIC, IPIs
from processors on the system bus, and self-generated interrupts. Interrupts can
Figure 10-1. Relationship of Local APIC and I/O APIC In Single-Processor Systems
I/O APIC
External
Interrupts
System Chip Set
System Bus
Processor Core
Local APIC
Pentium 4 and
Local
Interrupts
Bridge
PCI
Intel Xeon Processors
I/O APIC
External
Interrupts
System Chip Set
3-Wire APIC Bus
Processor Core
Local APIC
Pentium and P6
Local
Interrupts
Family Processors
Interrupt
Messages
Interrupt
Messages
Interrupt
Messages