Motorola CMD912x 用户手册
17
MCU_PORT 2
PK0
1 2
PK1
PK2
3 4
PK3
PK4
5 6
PK5
PB0/D0
7 8
PK7/ECS
PB2/D2
9 10 PB1/D1
PB4/D4 11 12 PB3/D3
PB6/D6 13 14 PB5/D5
PB6/D6 13 14 PB5/D5
PE0/XIRQ* 15 16 PB7/D7
PE6/MODB 17 18 PE3/LSTRB*
A14 19 20 PE5/MODA
A15 21 22 PE7
A16 23 24 A18
A17 25 26 A19
A15 21 22 PE7
A16 23 24 A18
A17 25 26 A19
The MCU_PORT 2 provides access to the
Expanded Bus and I/O lines of the HC12. Note:
Expanded Bus and I/O lines of the HC12. Note:
1) Not all I/O Ports are provided by all HC12
MCUs.
2) The A14 - A19 address signals are provided
by the PRU. The A16 - A19 signals are
derived from the HC12 PK0 - PK5 signals
when emulating internal flash paging
operation.
derived from the HC12 PK0 - PK5 signals
when emulating internal flash paging
operation.
BUS_PORT
GND
1 2
D11
D10
3 4
D12
D9
5 6
D13
D8
7 8
D14
A0
9 10 D15
A1 11 12 A2
A10 13 14 A3
/ OE 15 16 A4
A11 17 18 A5
A9 19 20 A6
A8 21 22 A7
A8 21 22 A7
A12 23 24 A13
/ WE
25 26 CS0
CS1 27 28 CS2
CS3 29 30 CS4
CS5 31 32 IRQ
CS3 29 30 CS4
CS5 31 32 IRQ
+5V 33 34 /P-SEL
/RW
35 36 CS6
E 37 38 CS7
GND 39 40 / RESET
The BUS_PORT supports off-board memory devices.
D8 - D15 High Byte Data Bus in Wide Expanded Mode and
Peripheral 8 bit data bus. Port A in Single Chip Mode.
Peripheral 8 bit data bus. Port A in Single Chip Mode.
A0 – A13 Memory Addresses 0 to 13.
/OE Memory Output Enable signal, Active Low. Valid with
ECLK and R/W high.
ECLK and R/W high.
CS0 – CS7 Peripheral chip selects, 16 bytes each, see
memory maps for location, 8 bit access (narrow bus).
memory maps for location, 8 bit access (narrow bus).
/WE Memory Write Enable signal, Active Low. Valid with
ECLK high and R/W low.
ECLK high and R/W low.
IRQ HC12 IRQ (PE1) Interrupt Input.
/RW HC12 Read/Write (PE2) control signal.
E HC12 ECLK (PE4) bus clock signal. Stretch should be
enabled in software.
enabled in software.
/P-SEL Selects Peripheral area, register following space, 8
bits wide.
bits wide.
/RESET HC12 active low RESET signal.