National Instruments NI 5401 用户手册

Chapter 1

Generating Functions with the NI 5401

1-4

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sine wave being generated and t

w

 is the pulse width of the SYNC output. 

The duty cycle is (t

w

/t

p

)

×

100%.

Figure 1-3.  SYNC Output and Duty Cycle

For your NI 5401 for PCI, you can route the SYNC output to the RTSI lines 
over the RTSI bus. For your NI 5401 for PXI, you can route the SYNC 
output to the TTL trigger lines over the TTL trigger bus. The SYNC output 
is derived from a comparator connected to the analog waveform and 
provides a meaningful waveform only when you are generating a sine wave 
on the ARB output. For more information on SYNC output, see Chapter 2, 

The PLL Ref connector is a phase-locked loop (PLL) input connector that 
can accept a reference clock from an external source and frequency lock the 
NI 5401 internal clock to this external clock. The reference clock should 
not deviate more than ±100 ppm from its nominal frequency. The minimum 
amplitude levels of 1 V

pk-pk

 are required on this clock. You can lock 

reference clock frequencies of 1 MHz and 5–20 MHz in 1 MHz steps.

You can frequency lock the NI 5401 for PCI to other National Instruments devices 

over the RTSI bus using the 20 MHz RTSI clock signal. You can frequency lock the 
NI 5401 for PXI to other National Instruments devices using the 10 MHz backplane clock.

If no external reference clock is available, the NI 5401 automatically tunes 
the internal clock to the highest accuracy possible. For more information on 
PLL operation, refer to Chapter 2,

ARB Output

t

p

SYNC Output
(50% Duty Cycle)

SYNC Output
(33% Duty Cycle)

t

w