National Instruments NI 5401 用户手册

Contents

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National Instruments Corporation

vii

NI 5401 User Manual

NI 5401 Block Diagram ........................................................................2-1

Waveform Data Path Block Diagram....................................................2-2

DDS Building Blocks ............................................................................2-3

Waveform Generation Trigger Sources ................................................2-5

Single Trigger Mode .............................................................................2-6

Continuous Trigger Mode .....................................................................2-6

Stepped Trigger Mode...........................................................................2-7

Analog Output and SYNC Out Block Diagram ....................................2-8

Waveform and Trigger Timings............................................................2-8

Output Attenuation Chain .....................................................................2-9

PLL Architecture for the NI 5401 for PCI ............................................2-12

PLL Architecture for the NI 5401 for PXI ............................................2-12

Analog Filter Correction .......................................................................2-13

RTSI Trigger Lines and Routing for the NI 5401 for PCI ....................2-14

PXI Trigger Lines, 10 MHz Backplane Oscillator, and
Routing for the NI 5401 for PXI ...........................................................2-14

Table

Digital Connector Signal Descriptions..................................................1-6