Cypress CY7C1386D 用户手册
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 38-05545 Rev. *E
Revised Feburary 09, 2007
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double-cycle deselect)
• Depth expansion without wait state
• 3.3V core power supply (V
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double-cycle deselect)
• Depth expansion without wait state
• 3.3V core power supply (V
DD
)
• 2.5V or 3.3V IO power supply (V
DDQ)
• Fast clock-to-output times
— 2.6 ns (for 250 MHz device)
• Provides high-performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel
• User selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• CY7C1386D/CY7C1387D available in JEDEC-standard
• Synchronous self timed writes
• Asynchronous output enable
• CY7C1386D/CY7C1387D available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball
FBGA package. CY7C1386F/CY7C1387F available in
Pb-free and non Pb-free 119-ball BGA package
FBGA package. CY7C1386F/CY7C1387F available in
Pb-free and non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
• ZZ sleep mode option
Functional Description
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
SRAM integrates 512K x 36/1M x 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive edge triggered clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining chip enable (CE
SRAM integrates 512K x 36/1M x 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive edge triggered clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining chip enable (CE
1
), depth
expansion chip enables (CE
2
and
CE
3
), burst control inputs
(ADSC, ADSP, and ADV), write enables (BW
X
, and BWE), and
global write (GW). Asynchronous inputs include the output
enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see
enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see
and
for further details). Write cycles can be
one to four bytes wide as controlled by the byte write control
inputs. GW active LOW causes all bytes to be written. This
device incorporates an additional pipelined enable register
which delays turning off the output buffers an additional cycle
when a deselect is executed.This feature allows depth
expansion without penalizing system performance.
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
operates from a +3.3V core power supply while all outputs
operate with a +3.3V or +2.5V supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
inputs. GW active LOW causes all bytes to be written. This
device incorporates an additional pipelined enable register
which delays turning off the output buffers an additional cycle
when a deselect is executed.This feature allows depth
expansion without penalizing system performance.
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
operates from a +3.3V core power supply while all outputs
operate with a +3.3V or +2.5V supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
3.0
3.4
ns
Maximum Operating Current
350
300
275
mA
Maximum CMOS Standby Current
70
70
70
mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on
www.cypress.com
.
2. CE
3
and CE
2
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in Single Chip Enable.