Cypress CY7C1170V18 用户手册
Document Number: 001-06620 Rev. *D
Revised March 06, 2008
Page 27 of 27
QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All
product and company names mentioned in this document are the trademarks of their respective holders.
product and company names mentioned in this document are the trademarks of their respective holders.
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
CY7C1168V18, CY7C1170V18
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Document Title: CY7C1166V18/CY7C1177V18/CY7C1168V18/CY7C1170V18, 18-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
Document Number: 001-06620
Architecture (2.5 Cycle Read Latency)
Document Number: 001-06620
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
430351
See ECN
NXR
New data sheet
*A
461654
See ECN
NXR
Revised the MPNs from
CY7C1177BV18 to CY7C1166V18
CY7C1168BV18 to CY7C1177V18
CY7C1170BV18 to CY7C1168V18
Changed t
CY7C1177BV18 to CY7C1166V18
CY7C1168BV18 to CY7C1177V18
CY7C1170BV18 to CY7C1168V18
Changed t
TH
and t
TL
from 40 ns to 20 ns, changed t
TMSS
, t
TDIS
, t
CS
, t
TMSH
, t
TDIH
,
t
CH
from
10 ns to 5 ns and changed t
TDOV
from 20 ns to 10 ns in TAP AC
Switching Characteristics table
Modified Power Up waveform
Modified Power Up waveform
*B
497629
See ECN
NXR
Changed the V
DDQ
operating voltage to 1.4V to V
DD
in the Features section, in
Operating Range table and in the DC Electrical Characteristics table
Added foot note in page 1
Changed the Maximum rating of Ambient Temperature with Power Applied from
–10°C to +85°C to –55°C to +125°C
Changed V
Added foot note in page 1
Changed the Maximum rating of Ambient Temperature with Power Applied from
–10°C to +85°C to –55°C to +125°C
Changed V
REF
(max) spec from 0.85V to 0.95V in the DC Electrical Character-
istics table and in the note below the table
Updated foot note 21 to specify Overshoot and Undershoot Spec
Updated
Updated foot note 21 to specify Overshoot and Undershoot Spec
Updated
Θ
JA
and
Θ
JC
values
Removed x9 part and its related information
Updated foot note 24
Updated foot note 24
*C
1175245
See ECN
VKN/KKVTMP Converted from preliminary to final
Added x8 and x9 parts
Updated logic block diagram for x18 and x36 parts
Changed I
Updated logic block diagram for x18 and x36 parts
Changed I
DD
values from 830 mA to 1080 mA for 400 MHz, 794 mA to 1020 mA
for 375 MHz, 733 mA to 920 mA for 333 MHz, 685 mA to 850 mA for 300 MHz
Changed I
Changed I
SB
values from 235 mA to 300 mA for 400 MHz, 227 mA to 290 mA
for 375 MHz, 212 mA to 260 mA for 333 MHz, 201 mA to 250 mA for 300 MHz
Changed t
Changed t
CYC(max)
spec to 8.4 ns for all speed bins
Changed
Θ
JA
value from 13.48 °C/W to 17.2 °C/W
Updated Ordering Information table
*D
2199066
See ECN
VKN/AESA
Added footnote# 19 related to I
DD