Kingston Technology 4GB 1333MHz DDR3 Non-ECC CL9 DIMM KVR1333D3N9K2/4G 数据表

产品代码
KVR1333D3N9K2/4G
下载
页码 2
KVR1333D3N9K2/4G
4GB (2GB 2Rx8 256M x 64-Bit x 2 pcs.)
PC3-10600 CL9 240-Pin DIMM Kit
DESCRIPTION
ValueRAM's KVR1333D3N9K2/4G is a kit of two 256M x 64-bit
(2GB) DDR3-1333 CL9 SDRAM (Synchronous DRAM), 2Rx8
memory modules, based on sixteen 128M x 8-bit DDR3-1333
FBGA components per module. Total kit capacity is 4GB. The
SPD's are programmed to JEDEC standard latency DDR3-1333
timing of 9-9-9 at 1.5V. Each 240-pin DIMM uses gold contact
fingers. The electrical and mechanical specifications are as
follows:
FEATURES
JEDEC standard 1.5V (1.425V ~1.575V) Power Supply
VDDQ = 1.5V (1.425V ~ 1.575V)
667MHz fCK for 1333Mb/sec/pin
8 independent internal bank
Programmable CAS Latency: 9, 8, 7, 6
Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
Bi-directional Differential Data Strobe
Internal(self) calibration: Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
Asynchronous Reset
PCB: Height 1.18” (30mm), double sided component
Document No. VALUERAM0673-001.B00     08/17/11     Page 1
Memory Module Specifi cations
*Power will vary depending on the SDRAM used.
SPECIFICATIONS
CL(IDD)
9 cycles
Row Cycle Time (tRCmin)
49.5ns (min.)
Refresh to Active/Refresh
110ns (min.)
Command Time (tRFCmin)
Row Active Time (tRASmin)
36ns (min.)
Power (Operating)
 1.620 W* (per module)
UL Rating
94 V - 0
Operating Temperature
0
o
 C to 85
o
 C
Storage Temperature
-55
o
 C to +100
o
 C
Continued >>
Important Information: The module defined in this data sheet is one of several configurations available under
this part number. While all configurations are compatible, the DRAM combination and/or the module height may
vary from what is described here.