Kingston Technology 4GB, 800MHz, DDR2, Non-ECC, Ultra Low-Lat CL4 (4-4-4-12), SODIMM (Kit of 2) KHX6400S2ULK2/4G 数据表
产品代码
KHX6400S2ULK2/4G
DESCRIPTION
Kingston's KHX6400S2ULK2/4G is a kit of two 256M x 64-bit
(2GB) CL4 ultra low latency SDRAM (Synchronous DRAM)
2Rx8 memory modules. Each module is based on sixteen 128M
x 8-bit DDR2 FBGA components. Total kit capacity is 4GB. The
SPDs are programmed to JEDEC ultra low latency timing of 4-
4-4-12 at 1.8V. Each 200-pin SODIMM uses gold contact
fingers and requires +1.8V. The electrical and mechanical
specifications are as follows:
Document No. 4805074-001.B00 06/30/11 Page 1
*Power will vary depending on the SDRAM used.
Memory Module Specifi cations
KHX6400S2ULK2/4G
4GB (2GB 256M x 64-Bit x 2 pcs.)
PC2-6400 CL4 200-Pin SODIMM Kit
PC2-6400 CL4 200-Pin SODIMM Kit
Continued >>
SPECIFICATIONS
Clock Cycle Time (tCK)
2.5ns (min.) / 8ns (max.)
Row Cycle Time (tRCmin)
57.5ns (min.)
Refresh to Active/Refresh
127.5ns (min.)
Command Time (tRFCmin)
Row Active Time (tRASmin)
45ns (min.) / 70,000 (max.)
Single Power Supply of
+1.8V (+/- .1V)
Power (Operating)
TBD* (per module)
UL Rating
94 V - 0
Operating Temperature
0
o
C to 55
o
C
Storage Temperature
-55
o
C to +125
o
C
FEATURES
•
Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
•
Double-data-rate architecture; two data transfers per
clock cycle
•
Bidirectional data strobe(DQS)
•
Differential clock inputs(CK and CK)
•
DLL aligns DQ and DQS transition with CK transition
•
Programmable Read latency 4, 3 (clock)
•
Burst Length: 4, 8 (Interleave/nibble sequential)
•
Programmable Burst type (sequential & interleave)
•
Timing Reference: 4-4-4-12 at +1.8V
•
Edge aligned data output, center aligned data input
•
Auto & Self refresh, 7.8us refresh interval (8K/64ms
refresh)
•
Serial presence detect with EEPROM
•
PCB : Height 1.180” (30.00mm), double sided
component