Intel Intel Core2 Extreme QX6850 HH80562XJ0808M 数据表
产品代码
HH80562XJ0808M
Electrical Specifications
22
Datasheet
2.6.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[3:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle.
identifies which signals are common clock, source synchronous,
and asynchronous.
Table 7.
FSB Signal Groups
Signal Group
Type
Signals
1
GTL+ Common
Clock Input
Clock Input
Synchronous to
BCLK[1:0]
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
GTL+ Common
Clock I/O
Clock I/O
Synchronous to
BCLK[1:0]
BCLK[1:0]
ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#, DBSY#,
DRDY#, HIT#, HITM#, LOCK#
DRDY#, HIT#, HITM#, LOCK#
GTL+ Source
Synchronous I/O
Synchronous I/O
Synchronous to
assoc. strobe
assoc. strobe
GTL+ Strobes
Synchronous to
BCLK[1:0]
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#, BSEL[2:],
VID[7:0]
STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#, BSEL[2:],
VID[7:0]
Open Drain
Output
Output
FERR#/PBE#, IERR#, THERMTRIP#, TDO
Open Drain
Input/Output
Input/Output
PROCHOT#
4
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]
2
Power/Other
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[3:0], COMP[8,3:0], RESERVED,
TESTHI[13,11:10,7:0], VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#
GTLREF[3:0], COMP[8,3:0], RESERVED,
TESTHI[13,11:10,7:0], VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#
2
, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
3
ADSTB0#
A[35:17]#
3
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#