Intel Intel Core2 Extreme QX6850 HH80562XJ0808M 数据表
产品代码
HH80562XJ0808M
Datasheet
29
Electrical Specifications
2.8
PECI DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors (may also include chipset components in the future) and
external thermal monitoring devices. The processor contains Digital Thermal Sensors
(DTS) distributed throughout die. These sensors are implemented as analog-to-digital
converters calibrated at the factory for reasonable accuracy to provide a digital
representation of relative processor temperature. PECI provides an interface to relay
the highest DTS temperature within a die to external management devices for thermal/
fan speed control. More detailed information is available in the Platform Environment
Control Interface (PECI) Specification.
NOTE:
1.
1.
V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
minimum/maximum
for V
TT
specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
3.
The input buffers use a Schmitt-triggered input design for improved noise immunity.
4.
One node is counted for each client and one node for the system host. Extended trace
lengths might appear as additional nodes.
lengths might appear as additional nodes.
§ §
Table 17.
PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes
V
in
Input Voltage Range
-0.30
V
TT
V
V
hysteresis
Hysteresis
0.1 * V
TT
—
V
3
V
n
Negative-edge threshold voltage
0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold voltage
0.550 * V
TT
0.725 * V
TT
V
I
source
High level output source
(V
(V
OH
= 0.75 * V
TT)
-6.0
N/A
mA
I
sink
Low level output sink
(V
(V
OL
= 0.25 * V
TT
)
0.5
1.0
mA
I
leak+
High impedance state leakage to V
tt
N/A
50
µA
2
I
leak-
High impedance leakage to GND
N/A
10
µA
2
C
bus
Bus capacitance per node
—
10
pF
4
V
noise
Signal noise immunity above 300 MHz
0.1 * V
TT
—
V
p-p