Philips P89LPC907 用户手册
Philips Semiconductors
User’s Manual - Preliminary -
P89LPC906/907/908
WATCHDOG TIMER
83
Figure 12-3: Watchdog Timer in Watchdog Mode (WDTE = 1)
WATCHDOG TIMER IN TIMER MODE
Figure 12-4 shows the Watchdog Timer in Timer Mode. In this mode, any changes to WDCON are written to the shadow register
after one watchdog clock cycle. A watchdog underflow will set the WDTOF bit. If IEN0.6 is set, the watchdog underflow is enabled
to cause an interrupt. WDTOF is cleared by writing a '0' to this bit in software. When an underflow occurs, the contents of WDL
is reloaded into the down counter and the watchdog timer immediately begins to count down again.
after one watchdog clock cycle. A watchdog underflow will set the WDTOF bit. If IEN0.6 is set, the watchdog underflow is enabled
to cause an interrupt. WDTOF is cleared by writing a '0' to this bit in software. When an underflow occurs, the contents of WDL
is reloaded into the down counter and the watchdog timer immediately begins to count down again.
A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs. Incorrect feeds are ignored
in this mode.
in this mode.
8-Bit Down
Counter
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
MOV WFEED2, #05AH
WDL (C1H)
PRE2
PRE1
PRE0
WDRUN
WDTOF
WDCLK
SHADOW
REGISTER FOR
WDCON
WDCON(A7H)
PRESCALER
RESET
control register
Watchdog reset can also be caused
by an invalid feed sequence, or by
writing to WDCON not immediately
followed by a feed sequence
Watchdog
Oscillator
PCLK
÷32