Philips P89LPC907 用户手册
Philips Semiconductors
User’s Manual - Preliminary -
P89LPC906/907/908
ADDITIONAL FEATURES
87
13. ADDITIONAL FEATURES
The AUXR1 register contains several special purpose control bits that relate to several chip features. AUXR1 is described in
Figure 13-1.
Figure 13-1.
Figure 13-1: AUXR1 Register
SOFTWARE RESET
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog
reset had occurred. If a value is written to AUXR1 that contains a 1 at bit position 3, all SFRs will be initialized and execution will
resume at program address 0000. Care should be taken when writing to AUXR1 to avoid accidental software resets.
reset had occurred. If a value is written to AUXR1 that contains a 1 at bit position 3, all SFRs will be initialized and execution will
resume at program address 0000. Care should be taken when writing to AUXR1 to avoid accidental software resets.
DUAL DATA POINTERS
The dual Data Pointers (DPTR) adds to the ways in which the processor can specify the address used with certain instructions.
The DPS bit in the AUXR1 register selects one of the two Data Pointers. The DPTR that is not currently selected is not accessible
to software unless the DPS bit is toggled.
The DPS bit in the AUXR1 register selects one of the two Data Pointers. The DPTR that is not currently selected is not accessible
to software unless the DPS bit is toggled.
Specific instructions affected by the Data Pointer selection are:
• INC
DPTR
Increments the Data Pointer by 1.
• JMP @A+DPTR
Jump indirect relative to DPTR value.
AUXR1
Address: A2h
Address: A2h
Not bit addressable
Reset Source(s): Any reset
Reset Value: 000000x0B
BIT
Reset Source(s): Any reset
Reset Value: 000000x0B
BIT
SYMBOL
FUNCTION
AUXR1.7
CLKLP
Clock Low Power Select. When set, reduces power consumption in the clock circuits. Can
be used when the clock frequency is 8MHz or less. After reset this bit is cleared to support
up to 12MHz operation (P89LPC906).
be used when the clock frequency is 8MHz or less. After reset this bit is cleared to support
up to 12MHz operation (P89LPC906).
AUXR1.6
EBRR
UART Break Detect Reset Enable. If ’1’, UART Break Detect will cause a chip reset
(P89LPC908). When writing to this register on the P89LPC906 or P89LPC907 devices,
this bit position should be written with a zero.
(P89LPC908). When writing to this register on the P89LPC906 or P89LPC907 devices,
this bit position should be written with a zero.
AUXR1.5
-
Reserved
AUXR1.4
-
Reserved
AUXR1.3
SRST
Software Reset. When set by software, resets the P89LPC906/907/908 as if a hardware
reset occurred.
reset occurred.
AUXR1.2
0
This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1,
without interfering with other bits in the register.
without interfering with other bits in the register.
AUXR1.1
-
Not used. Allowable to set to a "1" .
AUXR1.0
DPS
Data Pointer Select. Chooses one of two Data Pointers.
7
6
5
4
3
2
1
0
CLKLP
EBRR
-
-
SRST
0
-
DPS