National Instruments NI 5422 用户手册

Sample Clock 
Source

Sample Rate Range

Sample Rate Resolution

—

Divide-by-N

5 MS/s to 200 MS/s

Settable to (200 MS/s)/N
(1 

≤ N ≤ 40)

High 
Resolution

5 MS/s to 100 MS/s

>100 MS/s to 200 MS/s

1.06 µHz
4.24 µHz

CLK IN

5 MS/s to 200 MS/s

Resolution determined by 
external clock source.

External Sample Clock duty 
cycle tolerance 40% to 60%.

DDC CLK IN

5 MS/s to 200 MS/s

PXI Star 
Trigger

5 MS/s to 105 MS/s

PXI_Trig<0..7>

5 MS/s to 20 MS/s

Sample Clock 
Source

Delay Adjustment

Range

Delay Adjustment 

Resolution

—

Divide-by-N

±1 sample clock period

<5 ps

High-
Resolution
≤100 MHz

±1 sample clock period

Sample Clock 
Period/16,384

High-
Resolution
>100 MHz

±1 sample clock period

Sample Clock 

Period/4,096

External (all)

 0 ns to 7.6 ns

<15 ps

Table 2.   (Continued)