Renesas R5S72625 用户手册
Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00
Page 1383 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
11
ATTCHE
0
R/W
Connection Detection Interrupt Enable
Enables or disables the USB interrupt request when
the ATTCH interrupt is detected.
the ATTCH interrupt is detected.
0: Interrupt request disabled
1: Interrupt request enabled
10 to 7
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
6
EOFERRE
0
R/W
EOF Error Detection Interrupt Enable
Enables or disables the USB interrupt request when
the EOFERR interrupt is detected.
the EOFERR interrupt is detected.
0: Interrupt request disabled
1: Interrupt request enabled
5
SIGNE
0
R/W
Setup Transaction Error Interrupt Enable
Enables or disables the USB interrupt request when
the SIGN interrupt is detected.
the SIGN interrupt is detected.
0: Interrupt request disabled
1: Interrupt request enabled
4
SACKE
0
R/W
Setup Transaction Normal Response Interrupt
Enable
Enable
Enables or disables the USB interrupt request when
the SACK interrupt is detected.
the SACK interrupt is detected.
0: Interrupt request disabled
1: Interrupt request enabled
3 to 0
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
Note: The INTENB1 register bits can be set to 1 only when the host controller function is selected;
do not set these bits to 1 to enable the corresponding interrupt output when the function
controller function is selected.
controller function is selected.