Renesas R5S72623 用户手册
Section 2 CPU
R01UH0134EJ0400 Rev. 4.00
Page 73 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Classification
Types
Operation
Code
Code
Function
No. of
Instructions
Instructions
Floating-point
instructions
instructions
19
FSCHG
SZ bit inversion
48
FSQRT
Floating-point square root
FSTS
Floating-point
store
from system register FPUL
FSUB
Floating-point
subtraction
FTRC
Floating-point conversion with rounding to
integer
integer
FPU-related
CPU
instructions
CPU
instructions
2
LDS
Load into floating-point system register
8
STS
Store from floating-point system register
Bit
manipulation
manipulation
10 BAND Bit
AND
14
BCLR
Bit
clear
BLD
Bit
load
BOR
Bit
OR
BSET
Bit
set
BST
Bit
store
BXOR
Bit exclusive OR
BANDNOT Bit NOT AND
BORNOT
Bit NOT OR
BLDNOT
Bit NOT load
Total: 112
253