Renesas R5S72623 用户手册
Section 19 Serial I/O with FIFO
Page 960 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
2
1
0
BRDV2
BRDV1
BRDV0
0
0
0
R/W
R/W
R/W
Baud rate generator’s Division Ratio Setting
Set the frequency division ratio for the output stage of the
baud rate generator.
baud rate generator.
000: Prescalar output
1/2
001: Prescalar output
1/4
010: Prescalar output
1/8
011: Prescalar output
1/16
100: Prescalar output
1/32
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
The final frequency division ratio of the baud rate
generator is determined by BRPS
generator is determined by BRPS
BRDV (maximum
1/1024).
19.3.9
Transmit Data Assign Register (SITDAR)
SITDAR specifies the position of the transmit data in a frame (slot number).
Bit:
Initial Value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
TDLE
-
-
-
TDLA3 TDLA2 TDLA1 TDLA0
TDRE TLREP
-
-
TDRA3 TDRA2 TDRA1 TDRA0
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
15
TDLE
0
R/W
Transmit Left-Channel Data Enable
0: Disables left-channel data transmission
1: Enables left-channel data transmission
14 to 12
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.