Renesas R5S72622 用户手册
Section 32 General Purpose I/O Ports
Page 1680 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Table 32.4 Multiplexed Pins (Port C)
Setting Register
Setting Mode Bit (PCnMD[1:0])
00 01 10 11
Function 1
Function 2
Function 3
Function 4
PCCR2
PC10
TIOC2B
PC9
TIOC2A
PC8
CS3 TIOC4D
IRQ7
PCCR1 PC7 CKE TIOC4C
IRQ6
PC6
CAS TIOC4B
IRQ5
PC5
RAS TIOC4A
IRQ4
PC4
WE1/DQMU/WE
PCCR0 PC3
WE0/DQML
PC2 RD/
WR
PC1
RD
PC0
CS0
Table 32.5 Multiplexed Pins (Port D)
Setting Register
Setting Mode Bit (PDnMD[1:0])
00 01 10
Function 1
Function 2
Function 3
PDCR3 PD15
D15/NAF7 PWM2H
PD14 D14/NAF6
PWM2G
PD13 D13/NAF5
PWM2F
PD12 D12/NAF4
PWM2E
PDCR2 PD11
D11/NAF3 PWM2D
PD10 D10/NAF2
PWM2C
PD9 D9/NAF1
PWM2B
PD8 D8/NAF0
PWM2A
PDCR1 PD7
D7/
FWE PWM1H
PD6 D6/FALE
PWM1G
PD5 D5/FCLE
PWM1F
PD4
D4/
FRE PWM1E