Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 数据表
产品代码
P4X-UPE3210-316-6M1333
Datasheet
17
Introduction
1.1
Terminology
Figure 2.
Intel
®
3200 Chipset System Diagram Example
Term
Description
Chipset / Root
– Complex
– Complex
Used in this specification to refer to one or more hardware components that
connect processor complexes to the I/O and memory subsystems. The chipset
may include a variety of integrated devices.
connect processor complexes to the I/O and memory subsystems. The chipset
may include a variety of integrated devices.
CLink
Controller Link is a proprietary chip-to-chip connection between the MCH and
ICH. The chipset requires that Clink is connected in the platform.
ICH. The chipset requires that Clink is connected in the platform.
Core
The internal base logic in the MCH
DBI
Dynamic Bus Inversion
DDR2
A second generation Double Data Rate SDRAM memory technology
DDR2/3
C Link – Still
connect on non-
AMT system
DMI
DDR2/3
System Memory
CH A
CH B
PCI Express
PCI Express x8
USB 2. 0
12 Ports
GPIO
SATA
6 Ports
Firmware
SIO
Power
Management
Clock
Generation
SMBus 2.0 /
I
2
C
SST/PECI
(Fan Speed Control)
Gb LAN
WLAN
PCIe Bus
6 PCIe x1
Slots
PCI Bus
4 PCI Masters
Intel
®
ICH 9
Intel
®
3200
MCH
Processor
SPI
Flash
SPI
LPC
DDR2
DDR2