Renesas R5S72643 用户手册
Section 32 General Purpose I/O Ports
Page 1684 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Table 32.9 Multiplexed Pins (Port H)
Setting Register
Setting Mode Bit (PHnMD)
0 1
Function 1
Function 2
PHCR1
PH7
AN7
PH6
AN6
PH5
AN5
PH4
AN4
PHCR0 PH3
AN3
PH2 AN2
PH1 AN1
PH0
AN0
Table 32.10 Multiplexed Pins (Port J)
Setting Register
Setting Mode Bit (PJnMD[2:0])
000 001 010 011 100 101
Function 1 Function 2 Function 3
Function 4 Function 5 Function 6
PJCR2
PJ11
PWM2H
DACK1
PJ10
PWM2G
DREQ1
PJ9
PWM2F
TEND1
AUDIO_XOUT*
PJ8
PWM2E
RTS3
PJCR1
PJ7
TIOC1B
CTS3
PJ6
TIOC1A
SCK3
PJ5
IERxD
TxD3
PJ4
IETxD
RxD3
PJCR0 PJ3
CRx1
CRx0/CRx1 IRQ1
PJ2 CTx1
CTx0&CTx1
CS2 SCK0
LCD_M_DISP
PJ1 CRx0
IERxD
IRQ0
RxD0
PJ0
CTx0
IETxD
CS1 TxD0 A0