Renesas R5S72643 用户手册
Section 15 Serial Communication Interface with FIFO
Page 734 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Table 15.4 lists the sample SCBRR settings in asynchronous mode in which a base clock
frequency is 16 times the bit rate (the ABCS bit in SCEMR is 0) and the baud rate generator
operates in normal mode (the BGDM bit in SCEMR is 1), and table 15.5 lists the sample SCBRR
settings in clock synchronous mode.
frequency is 16 times the bit rate (the ABCS bit in SCEMR is 0) and the baud rate generator
operates in normal mode (the BGDM bit in SCEMR is 1), and table 15.5 lists the sample SCBRR
settings in clock synchronous mode.
Table 15.4 Bit Rates and SCBRR Settings (Asynchronous Mode, BGDM = 0, ABCS = 0)
Bit
Rate
(bits/s)
Rate
(bits/s)
P
(MHz)
24 28 32 36
n N Error
(
) n
N
Error (
) n N Error
(
) n N Error
(
)
110
3
106
–0.44
3
123
0.23 3
141
0.03 3
159
–0.12
150
3
77
0.16 3
90
0.16 3
103
0.16 3
116
0.16
300
2
155
0.16 3
45
–0.93
3
51
0.16 2
233
0.16
600 2 77 0.16
3 22 –0.93 3 25 0.16
2 116
0.16
1200
1
155
0.16 2
45
–0.93
2
51
0.16 1
233
0.16
2400 1 77 0.16
2 22 –0.93 2 25 0.16
1 116
0.16
4800
0
155
0.16 1
45
–0.93
1
51
0.16 0
233
0.16
9600 0 77 0.16
1 22 –0.93 1 25 0.16
0 116
0.16
19200
0 38 0.16
0 45 –0.93 0 51 0.16
0 58 –0.69
31250
0
23
0.00 0
27
0.00 0
31
0.00 0
35
0.00
38400
0 19 –2.34 0 22 –0.93 0 25 0.16
0 28 1.02
Note: The error rate should be
1 .