Intel Xeon E7420 AD80583QH0468M 数据表
产品代码
AD80583QH0468M
Thermal Specifications
102
Intel® Xeon® Processor 7400 Series Datasheet
6.3.1.1
T
CONTROL
and Tcc Activation on PECI-Based Systems
Fan speed control solutions based on PECI utilize a T
CONTROL
(Temperature Control
Offset) value stored in the processor IA32_TEMPERATURE_TARGET MSR. This MSR uses
the same offset temperature format as PECI, though it contains no sign bit. Thermal
management devices should infer the T
the same offset temperature format as PECI, though it contains no sign bit. Thermal
management devices should infer the T
CONTROL
value as negative. Thermal
management algorithms should utilize the relative temperature value delivered over
PECI in conjunction with the MSR value to control or optimize fan speeds. Figure 7-8
shows a conceptual fan control diagram using PECI temperatures.
PECI in conjunction with the MSR value to control or optimize fan speeds. Figure 7-8
shows a conceptual fan control diagram using PECI temperatures.
6.3.1.2
Processor Thermal Data Sample Rate and Filtering
The DTS (Digital Thermal Sensors) provide an improved capability to monitor device
hot spots, which inherently leads to more varying temperature readings over short time
intervals. The DTS sample interval range can be modified, and a data filtering algorithm
can be activated to help moderate this. The DTS sample interval range is 82 us
(default) to 20 ms (max). This value can be set in BIOS.
hot spots, which inherently leads to more varying temperature readings over short time
intervals. The DTS sample interval range can be modified, and a data filtering algorithm
can be activated to help moderate this. The DTS sample interval range is 82 us
(default) to 20 ms (max). This value can be set in BIOS.
To reduce the sample rate requirements on PECI and improve thermal data stability vs.
time the processor DTS also implements an averaging algorithm that filters the
incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed
mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) +
(new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on
by default and can be turned off in BIOS.
time the processor DTS also implements an averaging algorithm that filters the
incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed
mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) +
(new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on
by default and can be turned off in BIOS.
Host controllers should utilize the min/max sample times to determine the appropriate
sample rate based on the controller's fan control algorithm and targeted response rate.
The key items to take into account when settling on a fan control algorithm are the DTS
sample rate, whether the temperature filter is enabled, how often the PECI host will
poll the processor for temperature data, and the rate at which fan speed is changed.
Depending on the designer’s specific requirements the DTS sample rate and alpha-beta
filter may have no effect on the fan control algorithm.
sample rate based on the controller's fan control algorithm and targeted response rate.
The key items to take into account when settling on a fan control algorithm are the DTS
sample rate, whether the temperature filter is enabled, how often the PECI host will
poll the processor for temperature data, and the rate at which fan speed is changed.
Depending on the designer’s specific requirements the DTS sample rate and alpha-beta
filter may have no effect on the fan control algorithm.
Figure 6-9. Conceptual Fan Control Diagram For a PECI-Based Platform
Fan Speed
(RPM)
(not intended to depict actual implementation)
Max
Min
Temperature
PECI = -10
PECI = -20
TCC Activation
Temperature
T
CONTROL
Setting
PECI = 0
Fan Speed
(RPM)
(not intended to depict actual implementation)
Max
Min
Temperature
PECI = -10
PECI = -20
TCC Activation
Temperature
T
CONTROL
Setting
PECI = 0