Intel Pentium 4 BX80528JK180G 用户手册
产品代码
BX80528JK180G
Intel
®
Pentium
®
4 Processor in the 423-pin Package
8
(4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver
addresses two times per bus clock and is referred to as a ‘double-clocked’ or 2X address bus. In
addition, the Request Phase completes in one clock cycle. Working together, the 4X data bus and
2X address bus provide a data bus bandwidth of up to 3.2 Gbytes/second (3200Mbytes/sec).
Finally, the system bus also introduces transactions that are used to deliver interrupts.
addresses two times per bus clock and is referred to as a ‘double-clocked’ or 2X address bus. In
addition, the Request Phase completes in one clock cycle. Working together, the 4X data bus and
2X address bus provide a data bus bandwidth of up to 3.2 Gbytes/second (3200Mbytes/sec).
Finally, the system bus also introduces transactions that are used to deliver interrupts.
Signals on the system bus use Assisted GTL+ (AGTL+) level voltages which are fully described in
the Intel
the Intel
®
Pentium
®
4 Processor and Intel
®
850 Chipset Platform Design Guide.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“System bus” refers to the interface between the processor and system core logic (a.k.a. the chipset
components). The system bus is a interface to the processor, memory, and I/O. For this document,
“system bus” is used as the generic term for the Pentium 4 processor bus.
components). The system bus is a interface to the processor, memory, and I/O. For this document,
“system bus” is used as the generic term for the Pentium 4 processor bus.
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
•
Intel
®
Pentium
®
4 Processor in the 423-pin Package—The entire product including
processor core, integrated heat spreader, and interposer.
•
Pentium 4 processor—Throughout this document “Pentium 4 processor” refers to the Intel
®
Pentium
®
4 Processor in the 423-pin Package.
•
Interposer —The structure on which the processor core package and I/O pins are mounted.
•
Processor core —The processor’s execution engine. All AC timings and signal integrity
specifications are to the silicon of the processor core.
specifications are to the silicon of the processor core.
•
Integrated heat spreader —The surface used to make contact between a heatsink or other
thermal solution and the processor. Abbreviated as IHS.
thermal solution and the processor. Abbreviated as IHS.
•
423-Pin Socket —The connector which mates the Pentium 4 processor to the system board.
•
Retention mechanism —The support structure that is mounted on the system board to
provide added support and retention for heatsinks.
provide added support and retention for heatsinks.
•
OLGA (Organic Land Grid Array) Package —Microprocessor packaging using “flip chip”
design, where the processor is attached to the substrate face-down for better signal integrity,
more efficient heat removal and lower inductance.
design, where the processor is attached to the substrate face-down for better signal integrity,
more efficient heat removal and lower inductance.