Transcend 512MB DDR333 Unbuffer Non-ECC Memory TS64MLD64V3F5 用户手册
产品代码
TS64MLD64V3F5
T
T
T
S
S
S
6
6
6
4
4
4
M
M
M
L
L
L
D
D
D
6
6
6
4
4
4
V
V
V
3
3
3
F
F
F
5
5
5
184PIN DDR333 Unbuffered DIMM
512MB With 32Mx8 CL2.5
Transcend Information Inc.
1
Description
The TS64MLD64V3F5 is a 64Mx64bits Double Data Rate
SDRAM high density for DDR333. The TS64MLD64V3F5
consists of 16pcs CMOS 32Mx8 bits Double Data Rate
SDRAMs in 66 pin TSOP-II 400mil packages and a 2048
bits serial EEPROM on a 184-pin printed circuit board.
The TS64MLD64V3F5 is a Dual In-Line Memory Module
and is intended for mounting into 184-pin edge connector
sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• RoHS compliant products.
• Power supply: VDD: 2.5V ± 0.2V, VDDQ: 2.5V ±0.2V
• Max clock Freq: 166MHZ.
• Double-data-rate architecture; two data transfers per
• Power supply: VDD: 2.5V ± 0.2V, VDDQ: 2.5V ±0.2V
• Max clock Freq: 166MHZ.
• Double-data-rate architecture; two data transfers per
clock cycle
• Differential clock inputs (CK and /CK)
• Burst Mode Operation.
• Auto and Self Refresh.
• Data I/O transactions on both edge of data strobe.
• Edge aligned data output, center aligned data input.
• Serial Presence Detect (SPD) with serial EEPROM
• SSTL-2 compatible inputs and outputs.
• MRS cycle with address key programs.
• Burst Mode Operation.
• Auto and Self Refresh.
• Data I/O transactions on both edge of data strobe.
• Edge aligned data output, center aligned data input.
• Serial Presence Detect (SPD) with serial EEPROM
• SSTL-2 compatible inputs and outputs.
• MRS cycle with address key programs.
CAS Latency (Access from column address): 2.5
Burst Length (2, 4, 8 )
Data Sequence (Sequential & Interleave)
Placement
A
B
D
C
I
G
F
E
H
PCB : 09-1397