Intel Xeon X3460 BX80605X3460 用户手册

产品代码
BX80605X3460
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页码 296
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
107
Processor Integrated I/O (IIO) Configuration Registers
1
 
RO
0
Non Fatal Error Reporting Enable
Applies only to the PCI Express/DMI ports. Controls the reporting of non-fatal 
errors that IIO detects on the PCI Express/DMI interface or any non-fatal 
errors that PerfMon detect.
0 = Reporting of Non Fatal error detected by device is disabled.
1 = Reporting of Non Fatal error detected by device is enabled.
Refer to the latest PCI Express Base Specification for complete details of how 
this bit is used in conjunction with other bits to report errors.
For the PCI Express/DMI ports, this bit is not used to control the reporting of 
other internal component uncorrectable non-fatal errors (at the port unit) in 
any way.
0
RO
0
Correctable Error Reporting Enable
Applies only to the PCI Express/DMI ports. Controls the reporting of 
correctable errors that IIO detects on the PCI Express/DMI interface
0 = Reporting of link Correctable error detected by the port is disabled.
1 = Reporting of link Correctable error detected by port is enabled.
Refer to the latest PCI Express Base Specification for complete details of how 
this bit is used in conjunction with other bits to report errors.
For the PCI Express/DMI ports, this bit is not used to control the reporting of 
other internal component correctable errors (at the port unit) in any way.
 (Sheet 2 of 2)
Device:
8
Function:  0, 1, 2
Offset:
48h
Bit
Attr
Default
Description