Intel Xeon X3460 BX80605X3460 用户手册

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

111

Top of low memory. Note that bottom of low memory is assumed to be 0.

Top of high memory. Note that bottom of high memory is fixed at 4 GB.

Base address of Intel

 

QuickPath Interconnect non-coherent memory.

31:26

RWLB

0

TOLM Address
Indicates the top of low DRAM memory which is aligned to a 64-MB boundary. 

A 32-bit transaction that satisfies ‘0 ≤ A[31:26] ≤ TOLM[31:26]” is a transaction 

towards main memory.

25:0

RV

0

63:26

RWLB

0

TOHM Address
Indicates the limit of an aligned 64-MB granular region that decodes > 4-GB 

addresses towards system memory. A 64-bit transaction that satisfies ‘4G ≤ 

A[63:26] ≤ TOHM[63:26]” is a transaction towards main memory.
This register is programmed once at boot time and does not change after 

that, including any quiesce flows.

25:0

RV

0

63:26

RW

3F_FFFF_

FFFFh

Non-Coherent Memory Base Address
Describes the base address of a 64-MB aligned DRAM memory region on 

Intel

 

QuickPath Interconnect

 

that is non-coherent. Address bits [63:26] of 

an inbound address if it satisfies ‘NcMem.Base[63:26] <= A[63:26] <= 

NcMem.Limit[63:26]’ is considered to be towards the Intel

 

QuickPath 

Interconnect non-coherent memory region. It is expected that the range 

indicated by the Non-coherent memory base and limit registers is a subset 

of either the low DRAM or high DRAM memory regions as described using 

the corresponding base and limit registers.
This register is programmed once at boot time and does not change after 

that. 

25:0

RV

0