Intel Xeon X3460 BX80605X3460 用户手册
产品代码
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
291
System Address Map
5.8.2
Inbound Address Decoding
This section covers the decoding that is done on any transaction that is received on a
PCIe or DMI.
PCIe or DMI.
5.8.2.1
Overview
• All inbound addresses that fall above the top of Intel QuickPath Interconnect
physical address limit are flagged as errors by IIO. Top of Intel QuickPath
Interconnect physical address limit is dependent on the Intel QuickPath
Interconnect profile.
Interconnect physical address limit is dependent on the Intel QuickPath
Interconnect profile.
• Inbound decoding towards main memory in IIO happens in two steps. The first step
involves a ‘coarse decode’ towards main memory using two separate system
memory window ranges (0–TOLM, 4 GB–TOHM) that can be setup by software.
These ranges are non-overlapping. The second step is the fine source decode
towards an individual socket using the Intel QuickPath Interconnect memory source
address decoders.
memory window ranges (0–TOLM, 4 GB–TOHM) that can be setup by software.
These ranges are non-overlapping. The second step is the fine source decode
towards an individual socket using the Intel QuickPath Interconnect memory source
address decoders.
— A sub-region within one of the two coarse regions can be marked as non-
coherent
— VGA memory address would overlap one of the two main memory ranges and
IIO decoder is cognizant of that and steers these addresses towards the VGA
device of the system
• Inbound peer-to-peer decoding also happens in two steps. The first step involves
decoding peer-to-peer not crossing Intel QuickPath Interconnect (local peer-to-
peer). The second step involves actual target decoding for local peer-to-peer (if
transaction targets another device south of the IIO).
peer). The second step involves actual target decoding for local peer-to-peer (if
transaction targets another device south of the IIO).
— A pair of base/limit registers are provided for IIO to positively decode local
peer-to-peer transactions.
— On the processor, the global pair must be set to be the same as local, so the
second pair of base/limit registers do not add any functionality.
Note:
The processor IIO supports peer-2-peer writes, interrupt messages for legacy interrupt
and GPE (Please see section on Platform Interrupts in the Interrupt Chapter for more
details). The processor IIO does not support peer-2-peer reads.
— Fixed VGA memory addresses (A0000h–BFFFFh) are always peer-to-peer
addresses and would reside outside of the global peer-to-peer memory address
ranges mentioned above. The VGA memory addresses also overlap one of the
system memory address regions, but IIO always treats the VGA addresses as
peer-to-peer addresses. VGA I/O addresses (3B0h–3BBh, 3C0h–3DFh) always
are forwarded to the VGA I/O agent of the system. IIO performs only 16-bit
VGA I/O address decode inbound.
— Subtractively decoded inbound addresses are forwarded to the subtractive
decode port of the IIO.
• Inbound accesses to ME host visible devices (HECI, HECI2, IDEr, and KT; Dev18,
Fun0-3) are allowed and will not be blocked by IIO.
• Inbound accesses to FWH, TPM, VTCSR, CPUCSR and CPULocalCSR are blocked by
IIO (completer aborted).