Kingston Technology Memory 2GB 500MHz DDR Non-ECC Low-Latency CL3 Kit of 2 HyperX KHX4000LLK2/1G 数据表
产品代码
KHX4000LLK2/1G
Memory Module Specification
Document No. 4804438-001.A00
05/17/06
KHX4000LLK2/2G
2GB (128M x 64-Bit x 2 pcs.) PC4000
CL3 184-Pin DIMM Kit
KEY
ED
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DESCRIPTION:
Kingston's KHX4000LLK2/2G is a kit of two 128M x 64-bit 1GB (1024MB) PC4000 SDRAM
(Synchronous DRAM) CL3 memory modules. Total kit capacity is 2GB (2048MB). The components
on each module include sixteen 64M x 8-bit (16M x 8-bit x 4 Bank) DDR400 SDRAM in TSOP
packages. Each module pair has been tested to run at DDR 500MHz low latency timing of 3-3-3-8-1T
at 2.7V. The SPD is programmed to JEDEC standard latency 400Mhz timing of 3-3-3-8-1T at 2.6V.
Each 184-pin DIMM uses gold contact fingers and requires +2.6V. The electrical and mechanical
specifications are as follows:
(Synchronous DRAM) CL3 memory modules. Total kit capacity is 2GB (2048MB). The components
on each module include sixteen 64M x 8-bit (16M x 8-bit x 4 Bank) DDR400 SDRAM in TSOP
packages. Each module pair has been tested to run at DDR 500MHz low latency timing of 3-3-3-8-1T
at 2.7V. The SPD is programmed to JEDEC standard latency 400Mhz timing of 3-3-3-8-1T at 2.6V.
Each 184-pin DIMM uses gold contact fingers and requires +2.6V. The electrical and mechanical
specifications are as follows:
FEATURES:
Power supply : Vdd: 2.6V ± 0.1V, Vddq: 2.6V ± 0.1V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 3 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Timing Reference: 400MHz 3-3-3-8-1T at +2.6V / 500MHz 3-3-3-8-1T at +2.7V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
PCB : Height 1.250” (31.75mm), double sided component
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 3 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Timing Reference: 400MHz 3-3-3-8-1T at +2.6V / 500MHz 3-3-3-8-1T at +2.7V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
PCB : Height 1.250” (31.75mm), double sided component
PERFORMANCE:
Clock Cycle Time (tCK)
5ns (min.) / 10ns (max.)
Row Cycle Time (tRC)
55ns (min.)
Refresh Row Cycle Time (tRFC) 70ns (min.)
Row Active Time (tRAS)
Row Active Time (tRAS)
40ns (min.) / 70,000ns (max.)
Power
5.408 W (operating per module)
UL Rating
94 V - 0
Operating Temperature
0
o
C to 70
o
C
Storage Temperature
-55
o
C to +150
o
C
T E C H N O L O G Y