Integral INAFM16G40VSXE 用户手册
14
(Host terminating a Multiword DMA data burst)
Multiword DMA timing parameters
Mode 0
ns
Mode 1
ns
Mode2
ns
Note
t
0
Cycle time (min)
480
150
120
See note
t
D
DIOR-/DIOW- asserted pulse width (min)
215
80
70
See note
t
E
DIOR- data access (max)
150
60
50
t
F
DIOR- data hold (min)
5
5
5
t
G
DIOR-/DIOW- data setup (min)
100
30
20
t
H
DIOW- data hold (min)
20
15
10
t
I
DMACK to DIOR-/DIOW- setup (min)
0
0
0
t
J
DIOR-/DIOW- to DMACK hold (min)
20
5
5
t
KR
DIOR- negated pulse width (min)
50
50
25
See note
t
KW
DIOW- negated pulse width (min)
215
50
25
See note
t
LR
DIOR- to DMACK delay (max)
120
40
35
t
LW
DIOW- to DMACK delay (max)
40
40
35
t
M
CS(1:0) valid to DIOR-/DIOW- (min)
50
30
25
t
N
CS(1:0) hold (min)
15
10
10
t
Z
DMACK- to read data released (max)
20
25
25
Notes- t
0
is the minimum total cycle. t
D
is the minimum DIOR-/DIOW- assertion time, and t
K
(t
KR
or t
KW
,