Cisco Cisco UCS B260 M4 Blade Server 数据表

Each CPU controls three memory channels, as follows (refer to 

■

CPU1: Channels A, B, and C

— Bank 1 - A0, A1; B0, B1; C0, C1 (blue DIMM slots)

— Bank 2 - A4, A5; B4, B5; C4, C5 (black DIMM slots)

— Bank 3 - A2, A3; B2, B3; C2, C3 (blue DIMM slots)

— Bank 4 - A6, A7; B6, B7; C6, C7 (black DIMM slots)

■

CPU2: Channels D, E, and F

— Bank 1 - D0, D1; E0, E1; F0, F1 (blue DIMM slots)

— Bank 2 - D4, D5; E4, E5; F4, F5 (black DIMM slots)

— Bank 3 - D2, D3; E2, E3; F2, F3 (blue DIMM slots)

— Bank 4 - D6, D7; E6, E7; F6, F7 (black DIMM slots)

The DIMM and CPU physical layout is shown in 

. CPU 1 is located on right and CPU 2 on the left.