Cisco Cisco ASR 1000 Series 40Gbps SPA Interface Processor 数据表
© 2015 Cisco and/or its affiliates. All rights reserved. This document is Cisco Public Information.
Page 4 of 7
Product Specifications
Table 1 gives specifications of the Cisco 8-Port Channelized T1/E1 SPA Version 2.
Table 1.
Product Specifications
Features
Descriptions
Product compatibility
Cisco 7600 Series Routers
Cisco XR 12000 Series Routers
Cisco ASR 1000 Series Aggregation Services Routers
Cisco ASR 9000 Series Routers
Minimum software version
Cisco 7600 Series Routers - Cisco IOS
®
15.4(1)S
Cisco XR 12000 Series Routers - Cisco IOS XR 5.1.1
Cisco ASR 1000 Series Router - Cisco IOS XE 3.10.1
Cisco ASR 9000 Series Router - Cisco IOS XR 5.1.1
Port density per SPA
8 ports
Physical interface
● RJ-45 connector
● RJ-45 to BNC adapter cable option
● RJ-45 to BNC adapter cable option
Protocols
Encapsulation protocols:
● HDLC
● Point-to-Point Protocol (PPP), RFC 1662
● Frame Relay, RFC 1490
● Point-to-Point Protocol (PPP), RFC 1662
● Frame Relay, RFC 1490
Multilink support:
● MLPPP, RFC 1990
● MLFR, FRF.16
● LFI over Frame Relay (FRF.12) and MLPPP
● MLFR, FRF.16
● LFI over Frame Relay (FRF.12) and MLPPP
Features and functions
● Up to 8 independent T1 or E1 ports configurable as either all T1 or all E1 only
● Full-duplex connectivity
● Channelized and fractional T1/E1, clear channel E1 supported
● Up to 256 usable n x 64K, where n is 1 to 24 for T1 and 1 to 32 for E1
● Line-rate performance for all ports channelized to DS-0
● Integrated CSUs and DSUs
● Internal or network clocking selectable on each port
● Per-port, dual-color status LED
● Loopback capabilities:
● Full-duplex connectivity
● Channelized and fractional T1/E1, clear channel E1 supported
● Up to 256 usable n x 64K, where n is 1 to 24 for T1 and 1 to 32 for E1
● Line-rate performance for all ports channelized to DS-0
● Integrated CSUs and DSUs
● Internal or network clocking selectable on each port
● Per-port, dual-color status LED
● Loopback capabilities:
◦
Local and remote loopback at the T1 and E1 level
◦
Response to embedded loopback commands
◦
Insertion of loopback commands into transmitted signal
◦
N x DS-0 system-side loopback
● Bit-error-rate-testing (BERT) pattern generation and detection per channel (maximum of 6 T1/E1
at a time)
◦
Programmable pseudorandom pattern up to 32 bits long, including all 0s, all 1s, 211, 215, 220, 220
Quasi-Random Signal Sequence (QRSS), 223, alternating 0s and 1s, 1-in-8, and 3-in-24
Quasi-Random Signal Sequence (QRSS), 223, alternating 0s and 1s, 1-in-8, and 3-in-24
◦
32-bit error-count and bit-count registers
◦
Fully independent transmit and receive sections
◦
Detection of test patterns with bit error rates up to 10-2
● 24-hour history maintained for error statistics and failure counts, at 15-minute intervals
● 16- and 32-bit cyclic redundancy check (CRC); 16-bit default
● 16- and 32-bit cyclic redundancy check (CRC); 16-bit default