Intel X3450 BV80605001911AQ 用户手册

产品代码

BV80605001911AQ

Datasheet, Volume 1

3.1.3

Intel

VT-d Objectives ............................................................................32

3.1.4

Intel

VT-d Features...............................................................................32

3.1.5

Intel

VT-d Features Not Supported..........................................................33

3.2

Intel

Trusted Execution Technology (Intel

TXT) .................................................33

3.3

Intel

Hyper-Threading Technology .....................................................................34

3.4

Intel

Turbo Boost Technology ............................................................................34

Power Management .................................................................................................35
4.1

ACPI States Supported .......................................................................................35
4.1.1

System States........................................................................................35

4.1.2

Processor Core/Package Idle States...........................................................35

4.1.3

Integrated Memory Controller States .........................................................35

4.1.4

PCI Express* Link States .........................................................................36

4.1.5

Interface State Combinations ...................................................................36

4.2

Processor Core Power Management ......................................................................36
4.2.1

Enhanced Intel

SpeedStep

Technology ..................................................37

4.2.2

Low-Power Idle States.............................................................................37

4.2.3

Requesting Low-Power Idle States ............................................................39

4.2.4

Core C-states .........................................................................................39
4.2.4.1

Core C0 State ...........................................................................40

4.2.4.2

Core C1/C1E State ....................................................................40

4.2.4.3

Core C3 State ...........................................................................40

4.2.4.4

Core C6 State ...........................................................................40

4.2.4.5

C-State Auto-Demotion ..............................................................40

4.2.5

Package C-States ...................................................................................41
4.2.5.1

Package C0 ..............................................................................42

4.2.5.2

Package C1/C1E........................................................................42

4.2.5.3

Package C3 State ......................................................................43

4.2.5.4

Package C6 State ......................................................................43

4.3

IMC Power Management .....................................................................................43
4.3.1

Disabling Unused System Memory Outputs.................................................43

4.3.2

DRAM Power Management and Initialization ...............................................44
4.3.2.1

Initialization Role of CKE ............................................................44

4.3.2.2

Conditional Self-Refresh .............................................................44

4.3.2.3

Dynamic Power Down Operation..................................................44

4.3.2.4

DRAM I/O Power Management ....................................................45

4.4

PCI Express* Power Management ........................................................................45

Thermal Management ..............................................................................................47

Signal Description....................................................................................................49
6.1

System Memory Interface ...................................................................................50

6.2

Memory Reference and Compensation ..................................................................52

6.3

Reset and Miscellaneous Signals ..........................................................................52

6.4

PCI Express* Based Interface Signals ...................................................................53

6.5

DMI—Processor to PCH Serial Interface.................................................................53

6.6

PLL Signals .......................................................................................................54

6.7

Intel

Flexible Display Interface Signals ...............................................................54

6.8

JTAG/ITP Signals ...............................................................................................55

6.9

Error and Thermal Protection...............................................................................56