Intel X3450 BV80605001911AQ 用户手册
产品代码
BV80605001911AQ
Datasheet, Volume 1
13
Introduction
• PCI Express extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express Enhanced Access Mechanism. Accessing the device configuration space
in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X* Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X* Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
— PCI Express Port 0 -> PCI Express Port 1
— PCI Express Port 1 -> PCI Express Port 0
— DMI -> PCI Express Port 0
— DMI -> PCI Express Port 1
— PCI Express Port 1 -> DMI
— PCI Express Port 0 -> DMI
— PCI Express Port 1 -> PCI Express Port 0
— DMI -> PCI Express Port 0
— DMI -> PCI Express Port 1
— PCI Express Port 1 -> DMI
— PCI Express Port 0 -> DMI
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status.
• PCI Express reference clock is 100-MHz differential clock.
• Power Management Event (PME) functions.
• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.
• Dynamic frequency change capability (2.5 GT/s - 5.0 GT/s)
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
• Power Management Event (PME) functions.
• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.
• Dynamic frequency change capability (2.5 GT/s - 5.0 GT/s)
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
1.2.3
Direct Media Interface (DMI)
• Four lanes in each direction.
• 2.5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 2.5 GB/s, resulting in a real bandwidth per pair of
• 2.5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 2.5 GB/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
• Shares 100-MHz PCI Express reference clock.
• 64-bit downstream address format, but the processor never generates an address
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.