Intel Celeron 440 HH80557RG041512 数据表

24

Datasheet

NOTES:
1.

Refer to 

 for signal descriptions.

2.

In processor systems where no debug port is implemented on the system board, these 
signals are used to support a debug port interposer. In systems with the debug port 
implemented on the system board, these signals are no connects.

3.

The value of these signals during the active-to-inactive edge of RESET# defines the 
processor configuration options. See 

 for details.

4.

PROCHOT# signal type is open drain output and CMOS input.

.

NOTES:
1.

Signals that do not have R

TT

, nor are actively driven to their high-voltage level.

 

NOTE:
1.

These signals also have hysteresis added to the reference voltage. See 

 for more 

information.

Power/Other

VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, 
GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0], 
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, 
VSS_MB_REGULATION, DBR#

2

, VTT_OUT_LEFT, 

VTT_OUT_RIGHT, VTT_SEL, FCx, PECI

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#, 
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, 
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, 
HITM#, LOCK#, PROCHOT#, REQ[4:0]#, 
RS[2:0]#, TRDY#

A20M#, BCLK[1:0], BSEL[2:0], 
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0], 
LINT0/INTR, LINT1/NMI, PWRGOOD, 
RESET#, SMI#, STPCLK#, TESTHI[13:0], 
VID[6:0], GTLREF[1:0], TCK, TDI, TMS, 
TRST#

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, 
BR0#, TDO, VTT_SEL, FCx

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#, 
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#, 
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, 
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, 
TRDY#

A20M#, LINT0/INTR, LINT1/NMI, 
IGNNE#, INIT#, PROCHOT#, 
PWRGOOD

1

, SMI#, STPCLK#, TCK

1

, 

TDI

1

, TMS

1

, TRST#

1