Intel 220 LE80557RE009512 数据表
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产品代码
LE80557RE009512
Electrical Specifications
32
Datasheet
3.9
Clock Specifications
3.9.1
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to
for the processor supported
ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel Field representative.
NOTES:
1.
1.
Individual processors operate only at or below the rated frequency.
2.
Listed frequencies are not necessarily committed production frequencies.
§ §
Table 15.
Core Frequency to FSB Multiplier Configuration
Multiplication of System Core
Frequency to FSB Frequency
Core Frequency
(133 MHz BCLK/533 MHz FSB)
Notes
1, 2
1/9
1.20 GHz
-
1/10
1.33 GHz
-