Intel E7210 LF80564QH0568M 数据表
产品代码
LF80564QH0568M
Document Number: 318080-002
43
Electrical Specifications
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Not 100% tested. Specified by design characterization.
3.
This specification is based on the capabilities of the ITP debug port, not on processor silicon.
4.
Referenced to the rising edge of TCK.
5.
Referenced to the falling edge of TCK.
6.
TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
7.
Specification for a minimum swing defined between TAP V
t-
to V
t+
. This assumes a minimum edge rate of
0.5 V/ns.
8.
It is recommended that TMS be asserted while TRST# is being deasserted.
T57: TDI, TMS Hold Time
7.5
ns
4,7
T58: TDO Clock to Output Delay
0
7.5
ns
5
T59: TRST# Assert Time
2
T
TCK
6
Table 2-24. TAP Signal Group AC Specifications (Sheet 2 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
1, 2, 8