ASUS p3c-ls 用户手册

4. BIOS SETUP

This sets the operating state of the RDRAM devices in Pool B. Selecting
[Nap] allows the RDRAM in Pool B to enter power-saving mode. [Standby]
allows the RDRAM in Pool B to return to the working state quickly.

This sets the optimal SDRAM timings, depending on the memory modules
that you are using. The default setting of [By SPD] automatically adjusts
values in the CMOS chipset for maximum reliability and performance by
reading the contents in the SPD (Serial Presence Detect) device. The
EEPROM on the memory module stores critical parameter information about
the module, such as memory type, size, speed, voltage interface, and mod-
ule banks. [User Define] lets the user or BIOS set the SDRAM’s param-
eters. To avoid data integrity issues, such as data loss and/or data corrup-
tion, set to its default setting of [By SPD]. Configuration options: [User
Define] [By SPD]

When SDRAM Configuration is set to User Define

This controls the latency between the SDRAM read command and the time
that the data actually becomes available. NOTE: To display and access this
field, the SDRAM Configuration field must be set to [User Define].

This controls the latency between the SDRAM active command and the
read/write command. NOTE: To display and access this field, the
SDRAM Configuration field must be set to [User Define].

This controls the idle clocks after issuing a precharge command to the
SDRAM. NOTE: To display and access this field, the SDRAM Con-
figuration field must be set to [User Define].

This controls the leadoff clocks for CPU read cycles. Configuration op-
tions: [Fast] [Normal]

 Chip Configuration